型号 功能描述 生产厂家 企业 LOGO 操作
CD74HC107E.A

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . .

TI

德州仪器

Dual JK flip-flop with reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc

Philips

飞利浦

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Dual JK flip-flop with reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc

Philips

飞利浦

Dual JK flip-flop with reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc

Philips

飞利浦

更新时间:2025-9-27 9:32:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
TI
22+
14DIP
9000
原厂渠道,现货配单
Rochester
25+
电联咨询
7800
公司现货,提供拆样技术支持
TI/德州仪器
23+
SOP-14
10000
原厂授权一级代理,专业海外优势订货,价格优势、品种
24+
N/A
61000
一级代理-主营优势-实惠价格-不悔选择
Texas Instruments(德州仪器)
24+
14-DIP (0.300, 7.62mm)
690000
代理渠道/支持实单/只做原装
Texas Instruments
24+
14-DIP(0.300
56300
22+
5000
TI/德州仪器
24+
SOP
1436
只供应原装正品 欢迎询价
TI
23+
14DIP
9000
原装正品,支持实单
TI(德州仪器)
2021+
SOIC-14
499

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