4位口型锁存器

The CD4042 is a quad clocked “D” latch. It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. • Supply voltage range:3V to 15V \n• Temperature range:-40℃ to +125℃\n• Packaging information: DIP16/SOP16/SSOP16/TSSOP16;

CMOS 四路时钟控制“D”锁存器

CD4042B types contain four latch circuits, each strobed by a common clock. Complementary buffered outputs are available from each circuit. The impedance of the n- and p-channel output devices is balanced and all outputs are electrically identical.\n\n Information present at the data input is transfe • Clock polarity control\n• Common Clock\n• Standardized, symmetrical output characteristics\n• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n• Noise margin (full package-temperature range) =         1 V at VDD = 5 V         2 V at VDD = 10 V   ;

CMOS Quad D Latch, Clocked

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

CMOS Quad Clocked “D” Latch

Description CD4042BMS types contain four latch circuits, each strobed by a common clock. Complementary buffered outputs are available from each circuit. The impedance of the n- and p- channel output devices is balanced and all outputs are electrically identical. Applications • Buffer St

CMOS Quad Clocked D Latch

文件：197.52 Kbytes Page：3 Pages

CMOS Quad Clocked D Latch

文件：599.48 Kbytes Page：12 Pages

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes Page：30 Pages

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes Page：30 Pages

Quad Clocked D Latch

文件：124.27 Kbytes Page：6 Pages

CMOS Quad Clocked D Latch

文件：599.48 Kbytes Page：12 Pages

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes Page：30 Pages

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes Page：30 Pages

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes Page：30 Pages

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes Page：30 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC QUAD CLOCKED D LATCH 16SOIC 集成电路（IC） 锁存器

CMOS Quad Clocked D Latch

文件：599.48 Kbytes Page：12 Pages

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes Page：30 Pages

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes Page：30 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC QUAD CLOCKED D LATCH 16-SOIC 集成电路（IC） 锁存器

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes Page：30 Pages

CMOS Quad Clocked D Latch

文件：599.48 Kbytes Page：12 Pages

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes Page：30 Pages

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes Page：30 Pages

CMOS Quad Clocked D Latch

文件：599.48 Kbytes Page：12 Pages

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes Page：30 Pages

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes Page：30 Pages

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes Page：30 Pages

CMOS Quad Clocked D Latch

文件：599.48 Kbytes Page：12 Pages

CMOS Quad Clocked D Latch

文件：599.48 Kbytes Page：12 Pages

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes Page：30 Pages

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes Page：30 Pages

CMOS Quad Clocked D Latch

文件：599.48 Kbytes Page：12 Pages

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes Page：30 Pages

CMOS Quad Clocked D Latch

文件：599.48 Kbytes Page：12 Pages

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes Page：30 Pages

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes Page：30 Pages

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes Page：30 Pages

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes Page：30 Pages

CMOS Quad Clocked D Latch

文件：599.48 Kbytes Page：12 Pages

Quad Clocked D Latch

文件：124.27 Kbytes Page：6 Pages

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes Page：30 Pages

CMOS Quad Clocked D Latch

文件：599.48 Kbytes Page：12 Pages

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes Page：30 Pages

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes Page：30 Pages

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes Page：30 Pages

CMOS Quad Clocked D Latch

文件：599.48 Kbytes Page：12 Pages

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes Page：30 Pages

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes Page：30 Pages

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes Page：30 Pages

CMOS Quad Clocked D Latch

文件：599.48 Kbytes Page：12 Pages

Quadruple D-latch

DESCRIPTION The HEF4042B is a 4-bit latch with four data inputs (D0 to D3), four buffered latch outputs (O0 to O3), four buffered complementary latch outputs (O0 to O3) and two common enable inputs (E0 and E1). Information on D0 to D3 is transferred to O0 to O3 while both E0 and E1 are in the sam

QUAD CLOCKED D LATCH

Description The HCC4000B series is composed of close to 80 monolithic types built with Metal Oxide Complementary technology. It provides Designers with high voltage noise tolerant complete Logic series. It radiation hardness and immunity to Heavy Ions make this series to be usable in the

Quadruple D-latch

DESCRIPTION The HEF4042B is a 4-bit latch with four data inputs (D0 to D3), four buffered latch outputs (O0 to O3), four buffered complementary latch outputs (O0 to O3) and two common enable inputs (E0 and E1). Information on D0 to D3 is transferred to O0 to O3 while both E0 and E1 are in the sam

Quadruple D-latch

DESCRIPTION The HEF4042B is a 4-bit latch with four data inputs (D0 to D3), four buffered latch outputs (O0 to O3), four buffered complementary latch outputs (O0 to O3) and two common enable inputs (E0 and E1). Information on D0 to D3 is transferred to O0 to O3 while both E0 and E1 are in the sam

Quadruple D-latch

DESCRIPTION The HEF4042B is a 4-bit latch with four data inputs (D0 to D3), four buffered latch outputs (O0 to O3), four buffered complementary latch outputs (O0 to O3) and two common enable inputs (E0 and E1). Information on D0 to D3 is transferred to O0 to O3 while both E0 and E1 are in the sam

QUAD CLOCKED D LATCH

Quadruple Latch

Quadruple D-latch

Quadruple D-latch

Quad Transparent Latch

QUAD TRANSPARENT LATCH

QUAD TRANSPARENT LATCH

Quad Transparent Latch

Quad Transparent Latch