Quad Clocked D Latch

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Quadruple D-latch

DESCRIPTION The HEF4042B is a 4-bit latch with four data inputs (D0 to D3), four buffered latch outputs (O0 to O3), four buffered complementary latch outputs (O0 to O3) and two common enable inputs (E0 and E1). Information on D0 to D3 is transferred to O0 to O3 while both E0 and E1 are in the sam

Quad D latch

The BU4042B is a four-circuit D latch with a common clock line and separate data input terminals. When the polarity input is set to “H”, input (D) is presented to output (Q) as is, as long as the clock input is rising, and when the clock input falls, output (Q) holds input (D) at that point. Whil

Diffused Red and Green Indicator LED - 18mm Round

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RF Filter

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Wide Selection of Panel Seal Boots

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HIGH VOLTAGE CAPACITORS MONOLITHIC CERAMIC TYPE

Ceramic Stand-off Insulators for RF-Equipment

14-Stage Ripple Carry Binary Counters . 12-Stage Ripple Carry Binary Counters . 14-Stage Ripple Carry Binary Counters

14-Stage, 12-Stage Ripple Carry Binary Counters

CMOS RIPPLE-CARRY BINARY COUNTER DIVIDERS

CMOS RIPPLE-CARRY BINARY COUNTER DIVIDERS

14-Stage, 12-Stage Ripple Carry Binary Counters

RIPPLE-CARRY BINARY COUNTER/DIVIDERS

RIPPLE-CARRY BINARY COUNTER/DIVIDERS

12-bit Binary Counter

12-stage binary counter

12-stage binary counter

12-Bit Binary Counter

12-Bit Binary Counter

12−Bit Binary Counter

12-Bit Binary Counter

12−Bit Binary Counter

TWELVE STAGE BINARY COUNTER

12 Stage Ripple-Carry Binary Counter/Dividers

12 STAGE RIPPLE - CARRY BINARY COUNTER/DIVIDERS