CD4012B价格

参考价格:¥0.9534

型号:CD4012BE 品牌:TEXAS 备注:这里有CD4012B多少钱,2025年最近7天走势,今日出价,今日竞价,CD4012B批发/采购报价,CD4012B行情走势销售排行榜,CD4012B报价。
型号 功能描述 生产厂家 企业 LOGO 操作
CD4012B

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CD4012B

CMOS NAND GATES

文件:1.29026 Mbytes Page:20 Pages

TI

德州仪器

CD4012B

CMOS NAND GATES

文件:1.18484 Mbytes Page:19 Pages

TI

德州仪器

CD4012B

CMOS NAND GATES

文件:525.82 Kbytes Page:13 Pages

TI

德州仪器

CD4012B

2 通道、4 输入、3V 至 18V 与非门

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND Gates

Features • High-Voltage Types (20V Rating) • Propagation Delay Time = 60ns (typ.) at CL = 50pF, VDD = 10V • Buffered Inputs and Outputs • Standardized Symmetrical Output Characteristics • Maximum Input Current of 1A at 18V Over Full PackageTemperature Range; 100nA at 18V and +25oC • 100 Te

RENESAS

瑞萨

CMOS NAND Gates

Description CD4011BMS, CD4012BMS, and CD4023BMS NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. CD4011BMS - Quad 2 Input CD4012BMS - Dual 4 Input CD4023BMS - Triple 3 I

Intersil

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

文件:1.29026 Mbytes Page:20 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.18484 Mbytes Page:19 Pages

TI

德州仪器

CMOS NAND GATES

文件:525.82 Kbytes Page:13 Pages

TI

德州仪器

The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic dual-in-line ceramic packages

文件:523.01 Kbytes Page:12 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.29026 Mbytes Page:20 Pages

TI

德州仪器

CMOS NAND GATES

文件:525.82 Kbytes Page:13 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.18484 Mbytes Page:19 Pages

TI

德州仪器

封装/外壳:14-DIP(0.300",7.62mm) 包装:卷带(TR) 描述:IC GATE NAND 2CH 4-INP 14DIP 集成电路(IC) 门和反相器

TI2

德州仪器

The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic dual-in-line ceramic packages

文件:523.01 Kbytes Page:12 Pages

TI

德州仪器

CMOS NAND GATES

文件:525.82 Kbytes Page:13 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.18484 Mbytes Page:19 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.29026 Mbytes Page:20 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.18484 Mbytes Page:19 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.18484 Mbytes Page:19 Pages

TI

德州仪器

封装/外壳:14-SOIC(0.154",3.90mm 宽) 包装:管件 描述:IC GATE NAND 2CH 4-INP 14SOIC 集成电路(IC) 门和反相器

TI2

德州仪器

CMOS NAND GATES

文件:1.29026 Mbytes Page:20 Pages

TI

德州仪器

CMOS NAND GATES

文件:525.82 Kbytes Page:13 Pages

TI

德州仪器

The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic dual-in-line ceramic packages

文件:523.01 Kbytes Page:12 Pages

TI

德州仪器

CMOS NAND GATES

文件:525.82 Kbytes Page:13 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.18484 Mbytes Page:19 Pages

TI

德州仪器

The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic dual-in-line ceramic packages

文件:523.01 Kbytes Page:12 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.29026 Mbytes Page:20 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.29026 Mbytes Page:20 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.18484 Mbytes Page:19 Pages

TI

德州仪器

CMOS NAND GATES

文件:525.82 Kbytes Page:13 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.18484 Mbytes Page:19 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.29026 Mbytes Page:20 Pages

TI

德州仪器

CMOS NAND GATES

文件:525.82 Kbytes Page:13 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.29026 Mbytes Page:20 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.18484 Mbytes Page:19 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.29026 Mbytes Page:20 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.18484 Mbytes Page:19 Pages

TI

德州仪器

军用 2 通道 4 输入 3V 至 18V 与非门

TI

德州仪器

The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic dual-in-line ceramic packages

文件:523.01 Kbytes Page:12 Pages

TI

德州仪器

CMOS NAND GATES

文件:525.82 Kbytes Page:13 Pages

TI

德州仪器

CMOS NAND GATES

文件:525.82 Kbytes Page:13 Pages

TI

德州仪器

CMOS NAND GATES

文件:525.82 Kbytes Page:13 Pages

TI

德州仪器

The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic dual-in-line ceramic packages

文件:523.01 Kbytes Page:12 Pages

TI

德州仪器

替换型号 功能描述 生产厂家 企业 LOGO 操作

CMOS NAND Gates

Intersil

Dual 4-Input NOR(NAND) Gate

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

Dual 4-Input NOR(NAND) Gate

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

CMOS NAND GATES

TI

德州仪器

NAND GATES

STMICROELECTRONICS

意法半导体

NAND GATES

STMICROELECTRONICS

意法半导体

Dual 4-input NAND Gate

HitachiHitachi Semiconductor

日立日立公司

Dual 4-input NAND gate

Philips

飞利浦

Dual 4-input NAND gate

Philips

飞利浦

B-Suffix Series CMOS Gates

Motorola

摩托罗拉

B-Suffix Series CMOS Gates

Motorola

摩托罗拉

B-Suffix Series CMOS Gates

ONSEMI

安森美半导体

B−Suffix Series CMOS Gates

ONSEMI

安森美半导体

COMPLEMENTARY METAL OXIDE SILICON

NTE

INPUT NAND GATE

RANDE

C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC

TOSHIBA

东芝

CD4012B产品属性

  • 类型

    描述

  • 型号

    CD4012B

  • 制造商

    TI

  • 制造商全称

    Texas Instruments

  • 功能描述

    CMOS NAND GATES

更新时间:2025-9-26 13:52:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
ROHM/罗姆
24+
SOT23-4
17860
公司现货库存,支持实单
TI(德州仪器)
24+
标准封装
7443
原厂直销,大量现货库存,交期快。价格优,支持账期
TI(德州仪器)
24+
TSSOP14
2317
只做原装,提供一站式配单服务,代工代料。BOM配单
TI
24+
PDIP|14
798400
免费送样原盒原包现货一手渠道联系
NS/国半
24+
DIP14
37935
郑重承诺只做原装进口现货
TI
2+
DIP
5
原装现货
TI/德州仪器
2410+
DIP
50000
原装正品.假一赔百.正规渠道.原厂追溯.
NS
23+
DIP14
8
全新原装正品现货,支持订货
TI
06+
DIP
500
绝对全新原装正品,现货假壹赔佰
TI
24+
DIP
8500
只做原装正品假一赔十为客户做到零风险!!

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