位置:CD4012BE.A > CD4012BE.A详情

CD4012BE.A中文资料

厂家型号

CD4012BE.A

丝印代码

CD4012BE

封装外壳

PDIP

文件大小

1020.1Kbytes

页面数量

23

功能描述

CMOS NAND GATES

数据手册

下载地址一下载地址二到原厂下载

生产厂商

TI2

CD4012BE.A数据手册规格书PDF详情

Features:

Propagation delay time = 60 ns (typ.) at

CL =50 pF, Vpp = 10V

= Buffered inputs and outputs

= Standardized symmetrical output characteristics

Maximum input current of 1 uA at 18 V

over full package temperature range;

100 nA at 18 V and 25°C

= 100% tested for quiescent current at 20 V

5-V, 10-V, and 15-V parametric ratings

Noise margin (over full package temperature

range:

1VatVpp=5V

2VatVpp=10V

25VatVpp=15V

Meets all requirements of JEDEC Tentative

Standard No. 138, “Standard Specifications

for Description of “B” Series CMOS Devices”

更新时间:2026-5-20 9:32:00
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