QUAD 2-INPUT NAND BUFFERED B SERIES GATE

■ DESCRIPTION The UTC CD4011B contains four independent 2-input NAND gates which perform the function Y=A B • in positive logic. ■ FEATURES * 5V-10V-15V Parametric Ratings * Quad 2-Input NAND Gate * Symmetrical Output Characteristics * Maximum Input Current of 1uA at 15V Over Full Package Te

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS High Voltage Logic

Features High Input Voltage up to 20V Symmetrical Output Characteristics Max input current 1μA at 18V over full Military Temperature Range Low Power TTL compatible Specified at 5V, 10V & 15V Direct drop-in replacement for obsolete components in long term programs.

CMOS High Voltage Logic

文件：519.97 Kbytes Page：4 Pages

4路，2输入，3V至18V与非门

4000系列逻辑芯片

4 通道、2 输入、3V 至 18V 与非门

CMOS NAND GATES

文件：525.82 Kbytes Page：13 Pages

CMOS NAND GATES

文件：1.29026 Mbytes Page：20 Pages

CMOS NAND GATES

文件：1.18484 Mbytes Page：19 Pages

CMOS High Voltage Logic

Features High Input Voltage up to 20V Symmetrical Output Characteristics Max input current 1μA at 18V over full Military Temperature Range Low Power TTL compatible Specified at 5V, 10V & 15V Direct drop-in replacement for obsolete components in long term programs.

Quad 2-Input NOR Buffered B Series Gate . Quad 2-Input NAND Buffered B Series Gate

General Description The CD4001BC and CD4011BC quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also

Quad 2-Input NOR Buffered B Series Gate . Quad 2-Input NAND Buffered B Series Gate

General Description The CD4001BC and CD4011BC quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also

Quad 2-Input NOR Buffered B Series Gate . Quad 2-Input NAND Buffered B Series Gate

General Description The CD4001BC and CD4011BC quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also

Quad 2-Input NOR Buffered B Series Gate . Quad 2-Input NAND Buffered B Series Gate

General Description The CD4001BC and CD4011BC quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also

CMOS Quad 2-Input NAND Gate

Intersil’s Satellite Applications FlowTM (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

QUAD 2-INPUT NAND BUFFERED B SERIES GATE

■ DESCRIPTION The UTC CD4011B contains four independent 2-input NAND gates which perform the function Y=A B • in positive logic. ■ FEATURES * 5V-10V-15V Parametric Ratings * Quad 2-Input NAND Gate * Symmetrical Output Characteristics * Maximum Input Current of 1uA at 15V Over Full Package Te

CMOS Quad 2-Input NAND Gate

Intersil’s Satellite Applications FlowTM (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of

QUAD 2-INPUT NAND BUFFERED B SERIES GATE

■ DESCRIPTION The UTC CD4011B contains four independent 2-input NAND gates which perform the function Y=A B • in positive logic. ■ FEATURES * 5V-10V-15V Parametric Ratings * Quad 2-Input NAND Gate * Symmetrical Output Characteristics * Maximum Input Current of 1uA at 15V Over Full Package Te

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND Gates

Features • High-Voltage Types (20V Rating) • Propagation Delay Time = 60ns (typ.) at CL = 50pF, VDD = 10V • Buffered Inputs and Outputs • Standardized Symmetrical Output Characteristics • Maximum Input Current of 1A at 18V Over Full PackageTemperature Range; 100nA at 18V and +25oC • 100 Te

CMOS NAND Gates

Description CD4011BMS, CD4012BMS, and CD4023BMS NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. CD4011BMS - Quad 2 Input CD4012BMS - Dual 4 Input CD4023BMS - Triple 3 I

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS Quad 2-Input NAND Gate

Intersil’s Satellite Applications FlowTM (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of

CMOS NAND GATES

文件：1.18484 Mbytes Page：19 Pages

CMOS NAND GATES

文件：1.29026 Mbytes Page：20 Pages

Quad 2-Input NOR(NAND) Buffered B Series Gate

文件：164.76 Kbytes Page：6 Pages

Quad 2-Input NOR,NAND Buffered B Series Gate

文件：167.6 Kbytes Page：6 Pages

Quad 2-Input NOR,NAND Buffered B Series Gate

文件：167.6 Kbytes Page：6 Pages

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC GATE NAND 4CH 2-INP 14SOIC 集成电路（IC） 门和反相器

SEMICONDUCTORS

文件：2.43533 Mbytes Page：31 Pages

Quad 2-Input NOR,NAND Buffered B Series Gate

文件：167.6 Kbytes Page：6 Pages

封装/外壳：14-DIP（0.300"，7.62mm） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC GATE NAND 4CH 2-INP 14DIP 集成电路（IC） 门和反相器

The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic dual-in-line ceramic packages

文件：523.01 Kbytes Page：12 Pages

CMOS NAND GATES

文件：525.82 Kbytes Page：13 Pages

CMOS NAND GATES

文件：1.18484 Mbytes Page：19 Pages

CMOS NAND GATES

文件：1.29026 Mbytes Page：20 Pages

CMOS NAND GATES

文件：525.82 Kbytes Page：13 Pages

CMOS NAND GATES

文件：1.18484 Mbytes Page：19 Pages

CMOS NAND GATES

文件：1.29026 Mbytes Page：20 Pages

The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic dual-in-line ceramic packages

文件：523.01 Kbytes Page：12 Pages

Quad 2-input NAND gate

High Voltage CMOS Logic ICs

High Voltage CMOS Logic ICs

Quad 2-Input NOR(NAND) Buffered B Series Gate

Quad 2-Input NOR,NAND Buffered B Series Gate

CMOS NAND GATES

NAND GATES

NAND GATES

Quadruple 2-input NAND Gate

Quadruple 2-input NAND gate

Quadruple 2-input NAND gate

B-Suffix Series CMOS Gates

B-Suffix Series CMOS Gates

B−Suffix Series CMOS Gates

B-Suffix Series CMOS Gates

B-SUFFIX SERIES CMOS GATES

B-Suffix Series CMOS Gates

B-Suffix Series CMOS Gates

B-SUFFIX SERIES CMOS GATES

COMPLEMENTARY METAL OXIDE SILICON

INPUT NAND GATE

Quad 2 Input NAND Gate

QUAD 2 INPUT NAND GATE

C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC