The CD4011 NAND gates provide the system designer with direct implementation of the NAND function

Description The CD4011 NAND gates provide the system designer with direct implementation of the NAND function. Features ● Operating Voltage Range: 3.0 to 18 V ● Maximum input current of 1 at 18 V over full package- temperature range 100 nA at 18 V and 25 °C ● Noise margin (over full packa

SEMICONDUCTORS

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4通道与非门

4路2输入与非门，Quad 2-input Nand Gate

4路2输入与非门

CMOS NAND GATES

文件：525.82 Kbytes Page：13 Pages

Quad 2-Input NOR,NAND Buffered B Series Gate

文件：167.6 Kbytes Page：6 Pages

Quad 2-Input NOR(NAND) Buffered B Series Gate

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CMOS Decade Up-Down Counter/Latch/Display Driver

Features Separate clock-up and clock-down lines Capable of driving common cathode LEDs and other displays directly Allows cascading without any external circuitry 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18 V over full package- temperatu

CMOS Decade Up-Down Counter/Latch/Display Driver

Features Separate clock-up and clock-down lines Capable of driving common cathode LEDs and other displays directly Allows cascading without any external circuitry 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18 V over full package- temperatu

CMOS Decade Up-Down Counter/Latch/Display Driver

Features Separate clock-up and clock-down lines Capable of driving common cathode LEDs and other displays directly Allows cascading without any external circuitry 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18 V over full package- temperatu

CMOS HIGH-SPEED 8-BIT BIDIRECTIONAL CMOS/TTL INTERFACE LEVEL CONVERTER

CMOS HIGH-SPEED 8-BIT BIDIRECTIONAL CMOS/TTL INTERFACE LEVEL CONVERTER

Programmable Dual 4-Bit Terminator

Features: One standard “8” output will drive eight terminator circuits. Will terminate a CMOS data bus with up to 40 B~series inputs inputs or 3-stats outputs connected at Vop of 5 V. Input terminals protected by standard “B series ESD protection network. Preserves final logic state. Outp

Programmable Dual 4-Bit Terminator

Features: One standard “8” output will drive eight terminator circuits. Will terminate a CMOS data bus with up to 40 B~series inputs inputs or 3-stats outputs connected at Vop of 5 V. Input terminals protected by standard “B series ESD protection network. Preserves final logic state. Outp

Programmable Dual 4-Bit Terminator

Features: One standard “8” output will drive eight terminator circuits. Will terminate a CMOS data bus with up to 40 B~series inputs inputs or 3-stats outputs connected at Vop of 5 V. Input terminals protected by standard “B series ESD protection network. Preserves final logic state. Outp

CMOS NAND Gates

Features: Quiescent current specified to 15 V Maximum input leakage of 1 uA at 15 V (full package-temperature range) 1-V noise margin (full package-temperature range)

CMOS NAND Gates

Features: Quiescent current specified to 15 V Maximum input leakage of 1 uA at 15 V (full package-temperature range) 1-V noise margin (full package-temperature range)

CMOS NAND Gates

Features: Quiescent current specified to 15 V Maximum input leakage of 1 uA at 15 V (full package-temperature range) 1-V noise margin (full package-temperature range)

CMOS High Voltage Logic

Features High Input Voltage up to 20V Symmetrical Output Characteristics Max input current 1μA at 18V over full Military Temperature Range Low Power TTL compatible Specified at 5V, 10V & 15V Direct drop-in replacement for obsolete components in long term programs.

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

QUAD 2-INPUT NAND BUFFERED B SERIES GATE

■ DESCRIPTION The UTC CD4011B contains four independent 2-input NAND gates which perform the function Y=A B • in positive logic. ■ FEATURES * 5V-10V-15V Parametric Ratings * Quad 2-Input NAND Gate * Symmetrical Output Characteristics * Maximum Input Current of 1uA at 15V Over Full Package Te

CMOS High Voltage Logic

Features High Input Voltage up to 20V Symmetrical Output Characteristics Max input current 1μA at 18V over full Military Temperature Range Low Power TTL compatible Specified at 5V, 10V & 15V Direct drop-in replacement for obsolete components in long term programs.

Quad 2-Input NOR Buffered B Series Gate . Quad 2-Input NAND Buffered B Series Gate

General Description The CD4001BC and CD4011BC quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also

Quad 2-Input NOR Buffered B Series Gate . Quad 2-Input NAND Buffered B Series Gate

General Description The CD4001BC and CD4011BC quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also

Quad 2-Input NOR Buffered B Series Gate . Quad 2-Input NAND Buffered B Series Gate

General Description The CD4001BC and CD4011BC quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also

Quad 2-Input NOR Buffered B Series Gate . Quad 2-Input NAND Buffered B Series Gate

General Description The CD4001BC and CD4011BC quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also

CMOS Quad 2-Input NAND Gate

Intersil’s Satellite Applications FlowTM (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

QUAD 2-INPUT NAND BUFFERED B SERIES GATE

■ DESCRIPTION The UTC CD4011B contains four independent 2-input NAND gates which perform the function Y=A B • in positive logic. ■ FEATURES * 5V-10V-15V Parametric Ratings * Quad 2-Input NAND Gate * Symmetrical Output Characteristics * Maximum Input Current of 1uA at 15V Over Full Package Te

CMOS Quad 2-Input NAND Gate

Intersil’s Satellite Applications FlowTM (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of

QUAD 2-INPUT NAND BUFFERED B SERIES GATE

■ DESCRIPTION The UTC CD4011B contains four independent 2-input NAND gates which perform the function Y=A B • in positive logic. ■ FEATURES * 5V-10V-15V Parametric Ratings * Quad 2-Input NAND Gate * Symmetrical Output Characteristics * Maximum Input Current of 1uA at 15V Over Full Package Te

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND Gates

Features • High-Voltage Types (20V Rating) • Propagation Delay Time = 60ns (typ.) at CL = 50pF, VDD = 10V • Buffered Inputs and Outputs • Standardized Symmetrical Output Characteristics • Maximum Input Current of 1A at 18V Over Full PackageTemperature Range; 100nA at 18V and +25oC • 100 Te

CMOS NAND Gates

Description CD4011BMS, CD4012BMS, and CD4023BMS NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. CD4011BMS - Quad 2 Input CD4012BMS - Dual 4 Input CD4023BMS - Triple 3 I

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

CMOS Quad 2-Input NAND Gate

Intersil’s Satellite Applications FlowTM (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of

CMOS Quad 2-Input NAND Gate

Features: Propagation delay time = 30 ns (typ). at CL=50pF, Vpp=10V Standardized symmetrical output characteristics = 100% tested for quiescent current at 20V Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 5.V, 10-V, and 15-V p

CMOS Quad 2-Input NAND Gate

Features: Propagation delay time = 30 ns (typ). at CL=50pF, Vpp=10V Standardized symmetrical output characteristics = 100% tested for quiescent current at 20V Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 5.V, 10-V, and 15-V p

CMOS Quad 2-Input NAND Gate

Features: Propagation delay time = 30 ns (typ). at CL=50pF, Vpp=10V Standardized symmetrical output characteristics = 100% tested for quiescent current at 20V Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 5.V, 10-V, and 15-V p

CMOS Quad 2-Input NAND Gate

Features: Propagation delay time = 30 ns (typ). at CL=50pF, Vpp=10V Standardized symmetrical output characteristics = 100% tested for quiescent current at 20V Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 5.V, 10-V, and 15-V p

CMOS Quad 2-Input NAND Gate

Features: Propagation delay time = 30 ns (typ). at CL=50pF, Vpp=10V Standardized symmetrical output characteristics = 100% tested for quiescent current at 20V Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 5.V, 10-V, and 15-V p

Quad 2-input NAND gate

High Voltage CMOS Logic ICs

High Voltage CMOS Logic ICs

NAND GATES

NAND GATES

Quadruple 2-input NAND Gate

Quadruple 2-input NAND gate

Quadruple 2-input NAND gate

B-Suffix Series CMOS Gates

B-Suffix Series CMOS Gates

B-Suffix Series CMOS Gates

B−Suffix Series CMOS Gates

B-SUFFIX SERIES CMOS GATES

B-Suffix Series CMOS Gates

B-Suffix Series CMOS Gates

B-SUFFIX SERIES CMOS GATES

COMPLEMENTARY METAL OXIDE SILICON

INPUT NAND GATE

Quad 2 Input NAND Gate

QUAD 2 INPUT NAND GATE

C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC