1:1 Differential-to-LVDS Zero Delay Clock Generator

Features • One differential LVDS output pair and one differential feedback output pair • One differential clock input pair • CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL • Input frequency range: 62.5MHz to 1GHz • Output frequency range: 62.5MHz to

Differential-to-LVDS Zero Delay Clock Generator

1:1 Differential-to-LVDS Zero Delay Clock Generator

文件：401.42 Kbytes Page：17 Pages

丝印代码：ICS874S02BMILF；1:1 Differential-to-LVDS Zero Delay Clock Generator

Features • One differential LVDS output pair and one differential feedback output pair • One differential clock input pair • CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL • Input frequency range: 62.5MHz to 1GHz • Output frequency range: 62.5MHz to

1:1 Differential-to-LVDS Zero Delay Clock Generator

文件：401.42 Kbytes Page：17 Pages

1:1 Differential-to-LVDS Zero Delay Clock Generator

文件：401.42 Kbytes Page：17 Pages

One differential clock input pair

文件：4.08865 Mbytes Page：16 Pages