1:1 Differential-to-LVDS Zero Delay Clock Generator

Features • One differential LVDS output pair and one differential feedback output pair • One differential clock input pair • CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL • Input frequency range: 62.5MHz to 1GHz • Output frequency range: 62.5MHz to

1:1 Differential-to-LVDS Zero Delay Clock Generator

文件：401.42 Kbytes Page：17 Pages

封装/外壳：20-SOIC（0.295"，7.50mm 宽） 包装：托盘 描述：IC CLK GEN 1:1 DIFF ZD 20SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

1:1 Differential-to-LVDS Zero Delay Clock Generator

Features • One differential LVDS output pair and one differential feedback output pair • One differential clock input pair • CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL • Input frequency range: 62.5MHz to 1GHz • Output frequency range: 62.5MHz to

封装/外壳：20-SOIC（0.295"，7.50mm 宽） 包装：卷带（TR） 描述：IC CLK GEN 1:1 DIFF ZD 20SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

1:1 Differential-to-LVDS Zero Delay Clock Generator

1:1 Differential-to-LVDS Zero Delay Clock Generator

文件：401.42 Kbytes Page：17 Pages

1:1 Differential-to-LVDS Zero Delay Clock Generator

文件：401.42 Kbytes Page：17 Pages