Features

• One differential LVDS output pair and

one differential feedback output pair

• One differential clock input pair

• CLK/nCLK can accept the following differential input levels:

LVPECL, LVDS, LVHSTL, SSTL

• Input frequency range: 62.5MHz to 1GHz

• Output frequency range: 62.5MHz to 1GHz

• VCO range: 500MHz – 1GHz

• External feedback for zero delay clock regeneration with

configurable frequencies

• Programmable dividers allow for the following output-to-input

frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8

• Cycle-to-cycle jitter: 35ps (maximum)

• Static phase offset: ±100ps

• Full 3.3V supply mode

• -40°C to +85°C ambient operating temperature

• Available in lead-free packages