温度探头

Audio Cable, #22-1pr, TC, O/A Braid, CM

Product Description 22 AWG stranded (7x30) tinned copper conductors, PVC insulation, twisted pair, tinned copper spiral wrapped shield (85 coverage), PVC jacket.

MSD Module Selectors

文件：246.15 Kbytes Page：4 Pages

Low Skew, ÷1/÷2 Differential-to-3.3V LVPECL Clock Generator

FEATURES • 2 divide by 1 differential 3.3V LVPECL outputs; 2 divide by 2 differential 3.3V LVPECL outputs • Selectable differential CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • PCLK, nPCLK supports th

Low Skew Differential-to-3.3V LVPECL Clock Generator

GENERAL DESCRIPTION The 8737-11 is a low skew, high performance Differential-to-3.3V LVPECL Clock Generator/Divider. The 8737-11 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input level

Low Skew Differential-to-3.3V LVPECL Clock Generator

GENERAL DESCRIPTION The 8737-11 is a low skew, high performance Differential-to-3.3V LVPECL Clock Generator/Divider. The 8737-11 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input level

Low Skew, ÷1/÷2 Differential-to-3.3V LVPECL Clock Generator

FEATURES • 2 divide by 1 differential 3.3V LVPECL outputs; 2 divide by 2 differential 3.3V LVPECL outputs • Selectable differential CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • PCLK, nPCLK supports th

Low Skew ÷1/÷2 Differential-to- 3.3V LVPECL Clock Generator

FEATURES • Two divide by 1 differential 3.3V LVPECL outputs; Two divide by 2 differential 3.3V LVPECL outputs • Selectable differential CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • PCLK, nPCLK support

Low Skew ÷1/÷2 Differential-to- 3.3V LVPECL Clock Generator

FEATURES • Two divide by 1 differential 3.3V LVPECL outputs; Two divide by 2 differential 3.3V LVPECL outputs • Selectable differential CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • PCLK, nPCLK support

封装/外壳：20-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR） 描述：IC CLK BUFFER 2:2 650MHZ 20TSSOP 集成电路（IC） 时钟缓冲器，驱动器

Low Skew Differential-to- 3.3V LVPECL Clock Generator

文件：242.36 Kbytes Page：15 Pages

封装/外壳：20-TSSOP（0.173"，4.40mm 宽） 包装：托盘 描述：CLOCK FANOUT BUFFER (DISTRIBUTIO 集成电路（IC） 时钟发生器，PLL，频率合成器

Low Skew Differential-to- 3.3V LVPECL Clock Generator

文件：242.36 Kbytes Page：15 Pages

3-channel driver IC for optical disk drive

■ Overview The AN8737SB is a BTL type 3-channel driver IC, adopting a current feedback system for 2 channels, which makes it optimum for an actuator and a motor driver of CD-ROM/DVD-ROM. It can also constitute an optimum system in combination with the AN8488SB, a spindle plus loading driver IC. A

High efficiency, low noise, super low distortion, constant pitch volume, seventh generation K music.

文件：1.76375 Mbytes Page：28 Pages

High efficiency, low noise, super low distortion, constant pitch volume, seventh generation K music.

文件：1.76375 Mbytes Page：28 Pages