FEATURES

• 2 divide by 1 differential 3.3V LVPECL outputs;

2 divide by 2 differential 3.3V LVPECL outputs

• Selectable differential CLK, nCLK or LVPECL clock inputs

• CLK, nCLK pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

• PCLK, nPCLK supports the following input types:

LVPECL, CML, SSTL

• Maximum output frequency: 650MHz

• Translates any single ended input signal (LVCMOS, LVTTL,

GTL) to LVPECL levels with resistor bias on nCLK input

• Output skew: 60ps (maximum)

• Part-to-part skew: 200ps (maximum)

• Bank skew: Bank A - 20ps (maximum),

Bank B - 35ps (maximum)

• Additive phase jitter, RMS: 0.04ps (typical)

• Propagation delay: 1.7ns (maximum)

• 3.3V operating supply

• 0°C to 70°C ambient operating temperature

• Lead-Free package RoHS compliant