Low Skew ÷1/÷2 Differential-to- 3.3V LVPECL Clock Generator

FEATURES • Two divide by 1 differential 3.3V LVPECL outputs; Two divide by 2 differential 3.3V LVPECL outputs • Selectable differential CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • PCLK, nPCLK support

Low Skew Differential-to- 3.3V LVPECL Clock Generator

文件：242.36 Kbytes Page：15 Pages

封装/外壳：20-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR） 描述：IC CLK BUFFER 2:2 650MHZ 20TSSOP 集成电路（IC） 时钟缓冲器，驱动器

封装/外壳：20-TSSOP（0.173"，4.40mm 宽） 包装：托盘 描述：CLOCK FANOUT BUFFER (DISTRIBUTIO 集成电路（IC） 时钟发生器，PLL，频率合成器

Low Skew ÷1/÷2 Differential-to- 3.3V LVPECL Clock Generator

FEATURES • Two divide by 1 differential 3.3V LVPECL outputs; Two divide by 2 differential 3.3V LVPECL outputs • Selectable differential CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • PCLK, nPCLK support

Low Skew Differential-to- 3.3V LVPECL Clock Generator

文件：242.36 Kbytes Page：15 Pages