Customer Specification

Construction 1) Component 1 4 X 1 COND a) Conductor 24 (7/32) AWG Bare Copper 0.024 b) Insulation 0.016 Wall, Nom. TPES(Hytrel) 0.056 (1) Print ALPHANUMERIC NUMBERS - 1-ONE ALTERNATING AND INVERTED (2) Color Code Alpha Wire Color Code KX Cond Color Cond Color Cond Color 1 GREEN/YELL

1:4, Differential-to-LVCMOS/LVTTL Zero Delay Clock Generator

The 87004 is a highly versatile 1:4 Differentialto- LVCMOS/LVTTL Clock Generator and a member of the HiPerClockS® family of High Performance Clock Solutions from IDT. The 87004 has two selectable clock inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs can accept most standard differential input levels. • Four LVCMOS/LVTTL outputs, 7? typical output impedance\n• Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs\n• CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL\n• Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL levels on CLK0 and CLK1 in;

包装：散装 描述：B851 5.75HX3 BK/RD/WH 2-SIDE REV 标签，标志，护栏，标识 标签

包装：散装 描述：B851 5.75HX3 BK/RD/WH 2-SIDE REV 标签，标志，护栏，标识 标签

丝印代码：ICS87004AG；1:4, Differential-to-LVCMOS/LVT

Features • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs • CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL levels on CL

丝印代码：ICS87004AGLF；1:4, Differential-to-LVCMOS/LVT

Features • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs • CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL levels on CL

丝印代码：ICS87004AGLF；1:4, Differential-to-LVCMOS/LVT

Features • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs • CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL levels on CL

丝印代码：ICS87004AG；1:4, Differential-to-LVCMOS/LVT

Features • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs • CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL levels on CL

LVCMOS/LVTTL FANOUT BUFFER/DIVIDER Maximum output frequency: 250MHz

GENERAL DESCRIPTION The ICS87004I-03 is a low skew, ÷1, ÷2 ÷3, ÷4 ÷5, ÷6 ÷8, ÷16 LVCMOS/LVTTL Fanout Buffer/Divider and a member of theHiPerClockS™ family of High Performance Clock Solutions from IDT. The ICS87004I-03 has selectable clock inputs that accept single ended input levels. Output enabl

LVCMOS/LVTTL FANOUT BUFFER/DIVIDER Maximum output frequency: 250MHz

GENERAL DESCRIPTION The ICS87004I-03 is a low skew, ÷1, ÷2 ÷3, ÷4 ÷5, ÷6 ÷8, ÷16 LVCMOS/LVTTL Fanout Buffer/Divider and a member of theHiPerClockS™ family of High Performance Clock Solutions from IDT. The ICS87004I-03 has selectable clock inputs that accept single ended input levels. Output enabl

LVCMOS/LVTTL FANOUT BUFFER/DIVIDER Maximum output frequency: 250MHz

GENERAL DESCRIPTION The ICS87004I-03 is a low skew, ÷1, ÷2 ÷3, ÷4 ÷5, ÷6 ÷8, ÷16 LVCMOS/LVTTL Fanout Buffer/Divider and a member of theHiPerClockS™ family of High Performance Clock Solutions from IDT. The ICS87004I-03 has selectable clock inputs that accept single ended input levels. Output enabl

LVCMOS/LVTTL FANOUT BUFFER/DIVIDER Maximum output frequency: 250MHz

GENERAL DESCRIPTION The ICS87004I-03 is a low skew, ÷1, ÷2 ÷3, ÷4 ÷5, ÷6 ÷8, ÷16 LVCMOS/LVTTL Fanout Buffer/Divider and a member of theHiPerClockS™ family of High Performance Clock Solutions from IDT. The ICS87004I-03 has selectable clock inputs that accept single ended input levels. Output enabl

Customer Specification

Construction 1) Component 1 4 X 1 COND a) Conductor 24 (7/32) AWG Bare Copper 0.024 b) Insulation 0.016 Wall, Nom. TPES(Hytrel) 0.056 (1) Print ALPHANUMERIC NUMBERS - 1-ONE ALTERNATING AND INVERTED (2) Color Code Alpha Wire Color Code KX Cond Color Cond Color Cond Color 1 GREEN/YELL

LVCMOS/ LVTTL Fanout Buffer/Divider

The 87004I-03 is a low skew, ÷1, ÷2 ÷3, ÷4 ÷5, ÷6 ÷8, ÷16 LVCMOS/LVTTL Fanout Buffer/Divider. The 87004I-03 has selectable clock inputs that accept single ended input levels. Output enable pin controls whether the output is in the active or high impedance state. The 87004I-03 is characterized at 3.3 ·Two banks of two LVCMOS/LVTTL outputs\n·Selectable LVCMOS/LVTTL clock inputs\n·LVCMOS_CLK supports the following input types: LVCMOS, LVTTL\n·Maximum output frequency: 250MHz\n·Output skew: 40ps (typical)\n·Bank skew: 20ps (typical)\n·Part-to-part skew: 60ps (typical)\n·Power supply modes: CORE / O;

1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR

GENERAL DESCRIPTION The ICS87004 is a highly versatile 1:4 Differentialto-LVCMOS/LVTTL Clock Generator and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS87004 has two selectable clock inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs can accept most standard

1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR

GENERAL DESCRIPTION The ICS87004 is a highly versatile 1:4 Differentialto-LVCMOS/LVTTL Clock Generator and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS87004 has two selectable clock inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs can accept most standard

1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR

GENERAL DESCRIPTION The ICS87004 is a highly versatile 1:4 Differentialto-LVCMOS/LVTTL Clock Generator and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS87004 has two selectable clock inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs can accept most standard

Output frequency range

General Description The ICS87004I is a highly versatile 1:4 Differentialto-LVCMOS/LVTTL Clock Generator. The ICS87004I has two selectable clock inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs can accept most standard differential input levels. Internal bias on the nCLK0 and nCLK1 inputs allows the