1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR

GENERAL DESCRIPTION The ICS87004 is a highly versatile 1:4 Differentialto-LVCMOS/LVTTL Clock Generator and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS87004 has two selectable clock inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs can accept most standard

Customer Specification

Construction 1) Component 1 4 X 1 COND a) Conductor 24 (7/32) AWG Bare Copper 0.024 b) Insulation 0.016 Wall, Nom. TPES(Hytrel) 0.056 (1) Print ALPHANUMERIC NUMBERS - 1-ONE ALTERNATING AND INVERTED (2) Color Code Alpha Wire Color Code KX Cond Color Cond Color Cond Color 1 GREEN/YELL

1:4, Differential-to-LVCMOS/LVT

Features • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs • CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL levels on CL

1:4, Differential-to-LVCMOS/LVT

Features • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs • CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL levels on CL

1:4, Differential-to-LVCMOS/LVT

Features • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs • CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL levels on CL

1:4, Differential-to-LVCMOS/LVT

Features • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs • CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL levels on CL