Features

• Four LVCMOS/LVTTL outputs, 7Ω typical output impedance

• Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs

• CLKx/nCLKx pairs can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL

• Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL

levels on CLK0 and CLK1 inputs

• Output frequency range: 15.625MHz to 250MHz

• Input frequency range: 15.625MHz to 250MHz

• VCO range: 250MHz to 500MHz

• External feedback for “zero delay” clock regeneration with

configurable frequencies

• Programmable dividers allow for the following output-to-input

frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8

• Fully integrated PLL

• Cycle-to-cycle jitter: 45ps (maximum)

• Output skew: 50ps (maximum)

• Static phase offset: 50ps ± 125ps (3.3V ± 5), CLK0/nCLK0

• Full 3.3V or 2.5V output operating supply

• 5V tolerant inputs

• 0°C to 70°C ambient operating temperature

• Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages