T-1 Subminiature Lamps

T-1¼ Subminiature Lamps

AXL E EC DI16 M12 6P

文件：323.29 Kbytes Page：23 Pages

INDUCTORS Inductors Designed for Nationals 150 KHz SIMPLE SWITCHERTM

文件：100.28 Kbytes Page：1 Pages

包装：散装 描述：KNOB KNURLED 0.125\ 五金件，紧固件，配件 旋钮

M10X0.75 FEMALE THREAD DUST CAP W/ CHAIN

FEATURES M8 connector pin configurations: 3 pin, 4 pin, 5 pin, 6 pin Non-removable Contacts Meets IP67/IP68 water proof requirements -40°C to +85°C Temperature Range Available as loose piece or as pre-made M8 cables MATERIALS SHELL: Brass-Nickel Plated or Stainless Steel INSULATOR: PBT-B

Low Skew, 1-to-4, LVCMOS/LVTTL-to-LVDS Fanout Buffer

General Description The 854105 is a low skew, high performance 1-to-4 LVCMOS/LVTTL-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential Signaling (LVDS), the 854105 provides a low power, low noise solution for distributing clock signals over controlled impedances of 100. The 85410

Low Skew, 1-to-4, LVCMOS/ LVTTL-to-LVDS Fanout Buffer

General Description The 854105I is a low skew, high performance 1-to-4 LVCMOS/LVTTL-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential Signaling (LVDS), the 854105I provides a low power, low noise solution for distributing clock signals over controlled impedances of 100. The 854

Low Skew, 1-to-2 Differential-to-LVDS Fanout Buffer

FEATURES • Two differential LVDS outputs • One differential CLK, nCLK clock input • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 650MHz • Translates any single ended input signal to LVDS levels with resistor

2.5V Differential LVDS Clock Buffer

General Description The ICS854110I is a high-performance differential LVDS clock fanout buffer. The device is designed for signal fanout of high-frequency, low phase-noise clock signals. The selected differential input signal is distributed to ten differential LVDS outputs. The ICS854110I is char

2.5V Differential LVDS Clock Buffer

General Description The ICS854110I is a high-performance differential LVDS clock fanout buffer. The device is designed for signal fanout of high-frequency, low phase-noise clock signals. The selected differential input signal is distributed to ten differential LVDS outputs. The ICS854110I is char

2.5V Differential LVDS Clock Buffer

General Description The ICS854110I is a high-performance differential LVDS clock fanout buffer. The device is designed for signal fanout of high-frequency, low phase-noise clock signals. The selected differential input signal is distributed to ten differential LVDS outputs. The ICS854110I is char

2.5V Differential LVDS Clock Buffer

General Description The ICS854110I is a high-performance differential LVDS clock fanout buffer. The device is designed for signal fanout of high-frequency, low phase-noise clock signals. The selected differential input signal is distributed to ten differential LVDS outputs. The ICS854110I is char

Low Skew, 1-to-2 Differential-to-LVDS Fanout Buffer

FEATURES • Two differential LVDS outputs • One differential CLK, nCLK clock input • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 650MHz • Translates any single ended input signal to LVDS levels with resistor

Low Skew, 1-to-2 Differential-to-LVDS Fanout Buffer

FEATURES • Two differential LVDS outputs • One differential CLK, nCLK clock input • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 650MHz • Translates any single ended input signal to LVDS levels with resistor

Low Skew, 1-to-2 Differential-to-LVDS Fanout Buffer

FEATURES • Two differential LVDS outputs • One differential CLK, nCLK clock input • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 650MHz • Translates any single ended input signal to LVDS levels with resistor

Low Skew, 1-to-2 Differential-to-LVDS Fanout Buffer

FEATURES • Two differential LVDS outputs • One differential CLK, nCLK clock input • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 650MHz • Translates any single ended input signal to LVDS levels with resistor

Low Skew, 1-to-2 Differential-to-LVDS Fanout Buffer

FEATURES • Two differential LVDS outputs • One differential CLK, nCLK clock input • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 650MHz • Translates any single ended input signal to LVDS levels with resistor

包装：散装 描述：B302-10X14-YK-O-CAU-HAZARDOUS WA 标签，标志，护栏，标识 标志，铭牌，招贴

Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer

文件：321.31 Kbytes Page：15 Pages

Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer

文件：321.31 Kbytes Page：15 Pages

Low Skew,1-to-4,LVCMOS/LVTTL-to-LVDS Fanout Buffer

Low Skew,1-to-4,LVCMOS/LVTTL-to-LVDS Fanout Buffer

Low Skew,1-to-2 Differential-ToLVDS Fanout Buffer

Low Skew, 1-to-2 Different ial-to-LVDS Fanout Buffer

文件：230.58 Kbytes Page：15 Pages

Low Skew, 1-to-2 Different ial-to-LVDS Fanout Buffer

文件：228.99 Kbytes Page：15 Pages

Low Skew, 1-to-2 Different ial-to-LVDS Fanout Buffer

文件：228.99 Kbytes Page：15 Pages

Low Skew, 1-to-2 Different ial-to-LVDS Fanout Buffer

文件：230.58 Kbytes Page：15 Pages

Low Skew, 1-to-2 Different ial-to-LVDS Fanout Buffer

文件：228.99 Kbytes Page：15 Pages

Reasons for reissue of this instruction sheet are provided in Section 8, REVISION SUMMARY.

文件：224.38 Kbytes Page：5 Pages

Feed- Through Head Assembly

文件：142.31 Kbytes Page：5 Pages

General Purpose CMOS Rail-to-Rail Amplifiers

GENERAL DESCRIPTION The AD8541/AD8542/AD8544 are single, dual, and quad rail to-rail input and output, single-supply amplifiers featuring very low supply current and 1 MHz bandwidth. All are guaranteed to operate from a 2.7 V single supply as well as a 5 V supply. These parts provide 1 MHz bandwi

General-Purpose CMOS Rail-to-Rail Amplifiers

文件：430.46 Kbytes Page：20 Pages