Low Skew, 1-to-2 Differential-to-LVDS Fanout Buffer

FEATURES • Two differential LVDS outputs • One differential CLK, nCLK clock input • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 650MHz • Translates any single ended input signal to LVDS levels with resistor

Low Skew,1-to-2 Differential-ToLVDS Fanout Buffer

Low Skew, 1-to-2 Different ial-to-LVDS Fanout Buffer

文件：228.99 Kbytes Page：15 Pages

Low Skew, 1-to-2 Differential-to-LVDS Fanout Buffer

FEATURES • Two differential LVDS outputs • One differential CLK, nCLK clock input • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 650MHz • Translates any single ended input signal to LVDS levels with resistor

Low Skew, 1-to-2 Different ial-to-LVDS Fanout Buffer

文件：230.58 Kbytes Page：15 Pages

Low Skew, 1-to-2 Differential-to-LVDS Fanout Buffer

FEATURES • Two differential LVDS outputs • One differential CLK, nCLK clock input • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 650MHz • Translates any single ended input signal to LVDS levels with resistor

Low Skew, 1-to-2 Different ial-to-LVDS Fanout Buffer

文件：228.99 Kbytes Page：15 Pages

Low Skew, 1-to-2 Different ial-to-LVDS Fanout Buffer

文件：228.99 Kbytes Page：15 Pages