Low Skew, 1-to-8, Differential-to-LVDS Clock

Features • Eight differential LVDS output pairs • CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to LVDS levels without external bias netw

Low Skew,1-to-8,Differential-to-LVDS Clock

The 85408 is a low skew, high performance 1-to-8 Differential-to-LVDS Clock Distribution Chip from IDT. The 85408 CLK, nCLK pair can accept most differential input levels and translates them to 3.3V LVDS output levels. Utilizing Low Voltage Differential Signaling (LVDS), the 85408 provides a low pow • Eight differential LVDS output pairs\n• CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL\n• Maximum output frequency: 700MHz\n• Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to LVDS levels without external bias networks\n• Transl;

包装：散装 描述：B302-10X14-YK-O-CAU-HAZARDOUS WA 标签，标志，护栏，标识 标志，铭牌，招贴

包装：散装 描述：B302-10X14-YK-O-CAU-HAZARDOUS WA 标签，标志，护栏，标识 标志，铭牌，招贴

丝印代码：ICS85408BGILF；Low Skew, 1-to-8, Differential-to-LVDS Clock

Features • Eight differential LVDS output pairs • One differential clock input pair • CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to

丝印代码：ICS85408BGILF；Low Skew, 1-to-8, Differential-to-LVDS Clock

Features • Eight differential LVDS output pairs • One differential clock input pair • CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to

丝印代码：ICS85408BGLF；Low Skew, 1-to-8, Differential-to-LVDS Clock

Features • Eight differential LVDS output pairs • CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to LVDS levels without external bias netw

丝印代码：ICS85408BGLF；Low Skew, 1-to-8, Differential-to-LVDS Clock

Features • Eight differential LVDS output pairs • CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to LVDS levels without external bias netw

Low Skew, 1-to-8, Differential-to-LVDS Clock

Features • Eight differential LVDS output pairs • One differential clock input pair • CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to

Low Skew,1-to-8,Differential-to-LVDS Clock

The 85408I is a low skew, high performance 1-to-8 Differential-to-LVDS Clock Distribution Chip and a member of the family of High Performance Clock Solutions from IDT. The 85408I CLK, nCLK pair can accept most differential input levels and translates them to 3.3V LVDS output levels. Utilizing Low Vo • Eight differential LVDS output pairs\n• CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL\n• Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to LVDS levels without external bias networks\n• Multiple output enable inputs for disablin;

Low Skew, 1-to-8, Differential-to-LVDS Clock

文件：299.34 Kbytes Page：16 Pages

丝印代码：ICS85408BGILF；Low Skew, 1-to-8 , Different ial-to-LVDS Clock

文件：299.2 Kbytes Page：16 Pages

丝印代码：ICS85408BGILF；Low Skew, 1-to-8 , Different ial-to-LVDS Clock

文件：299.2 Kbytes Page：16 Pages

丝印代码：ICS85408BGLF；Low Skew, 1-to-8, Differential-to-LVDS Clock

文件：299.34 Kbytes Page：16 Pages

丝印代码：ICS85408BGLF；Low Skew, 1-to-8, Differential-to-LVDS Clock

文件：299.34 Kbytes Page：16 Pages

Low Skew, 1-to-8 , Different ial-to-LVDS Clock

文件：299.2 Kbytes Page：16 Pages

LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

GENERAL DESCRIPTION The ICS85408 is a low skew, high performance 1-to-8 Differential-to-LVDS Clock Distribution Chip and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS85408 CLK, nCLK pair can accept most differential input levels and translates them to 3

LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

GENERAL DESCRIPTION The ICS85408 is a low skew, high performance 1-to-8 Differential-to-LVDS Clock Distribution Chip and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS85408 CLK, nCLK pair can accept most differential input levels and translates them to 3

LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

GENERAL DESCRIPTION The ICS85408 is a low skew, high performance 1-to-8 Differential-to-LVDS Clock Distribution Chip and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS85408 CLK, nCLK pair can accept most differential input levels and translates them to 3

LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

GENERAL DESCRIPTION The ICS85408 is a low skew, high performance 1-to-8 Differential-to-LVDS Clock Distribution Chip and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS85408 CLK, nCLK pair can accept most differential input levels and translates them to 3

LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

GENERAL DESCRIPTION The ICS85408 is a low skew, high performance 1-to-8 Differential-to-LVDS Clock Distribution Chip and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS85408 CLK, nCLK pair can accept most differential input levels and translates them to 3