LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

GENERAL DESCRIPTION The ICS85408 is a low skew, high performance 1-to-8 Differential-to-LVDS Clock Distribution Chip and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS85408 CLK, nCLK pair can accept most differential input levels and translates them to 3

LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

GENERAL DESCRIPTION The ICS85408 is a low skew, high performance 1-to-8 Differential-to-LVDS Clock Distribution Chip and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS85408 CLK, nCLK pair can accept most differential input levels and translates them to 3

LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

GENERAL DESCRIPTION The ICS85408 is a low skew, high performance 1-to-8 Differential-to-LVDS Clock Distribution Chip and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS85408 CLK, nCLK pair can accept most differential input levels and translates them to 3

LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

GENERAL DESCRIPTION The ICS85408 is a low skew, high performance 1-to-8 Differential-to-LVDS Clock Distribution Chip and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS85408 CLK, nCLK pair can accept most differential input levels and translates them to 3

Low Skew, 1-to-8, Differential-to-LVDS Clock

Features • Eight differential LVDS output pairs • CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to LVDS levels without external bias netw

Low Skew, 1-to-8, Differential-to-LVDS Clock

Features • Eight differential LVDS output pairs • One differential clock input pair • CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to

Low Skew, 1-to-8, Differential-to-LVDS Clock

Features • Eight differential LVDS output pairs • One differential clock input pair • CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to

Low Skew, 1-to-8 , Different ial-to-LVDS Clock

文件：299.2 Kbytes Page：16 Pages

Low Skew, 1-to-8 , Different ial-to-LVDS Clock

文件：299.2 Kbytes Page：16 Pages