Low Skew, 1-to-8, Differential-to-LVDS Clock

Features • Eight differential LVDS output pairs • One differential clock input pair • CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to

Low Skew,1-to-8,Differential-to-LVDS Clock

Low Skew, 1-to-8 , Different ial-to-LVDS Clock

文件：299.2 Kbytes Page：16 Pages

Low Skew, 1-to-8, Differential-to-LVDS Clock

Features • Eight differential LVDS output pairs • CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to LVDS levels without external bias netw

Low Skew, 1-to-8, Differential-to-LVDS Clock

Features • Eight differential LVDS output pairs • One differential clock input pair • CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to

Low Skew, 1-to-8, Differential-to-LVDS Clock

Features • Eight differential LVDS output pairs • One differential clock input pair • CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to

Low Skew, 1-to-8 , Different ial-to-LVDS Clock

文件：299.2 Kbytes Page：16 Pages

Low Skew, 1-to-8 , Different ial-to-LVDS Clock

文件：299.2 Kbytes Page：16 Pages