位置：首页 > IC中文资料第3426页 > 74LVQ373
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
74LVQ373 | OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING DESCRIPTION The 74LVQ373 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. These 8 bit D-Type latch are controlled by a latc | STMICROELECTRONICS 意法半导体 |   | |
74LVQ373 | Low Voltage Octal Transparent Latch with 3-STATE Outputs General Description The LVQ373 consists of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on the bus whe | Fairchild 仙童半导体 | | |
74LVQ373 | LOW VOLTAGE CMOS OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING 文件：289.17 Kbytes Page：13 Pages | STMICROELECTRONICS 意法半导体 | | |
74LVQ373 | Low Voltage Octal Transparent Latch with 3-STATE Outputs | ONSEMI 安森美半导体 | | |
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING DESCRIPTION The 74LVQ373 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. These 8 bit D-Type latch are controlled by a latc | STMICROELECTRONICS 意法半导体 | | ||
Low Voltage Octal Transparent Latch with 3-STATE Outputs General Description The LVQ373 consists of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on the bus whe | Fairchild 仙童半导体 | | ||
Low Voltage Octal Transparent Latch with 3-STATE Outputs General Description The LVQ373 consists of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on the bus whe | Fairchild 仙童半导体 | | ||
Low Voltage Octal Transparent Latch with 3-STATE Outputs General Description The LVQ373 consists of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on the bus whe | Fairchild 仙童半导体 | | ||
Low Voltage Octal Transparent Latch with 3-STATE Outputs General Description The LVQ373 consists of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on the bus whe | Fairchild 仙童半导体 | | ||
Low Voltage Octal Transparent Latch with 3-STATE Outputs General Description The LVQ373 consists of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on the bus whe | Fairchild 仙童半导体 | | ||
Low Voltage Octal Transparent Latch with 3-STATE Outputs General Description The LVQ373 consists of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on the bus whe | Fairchild 仙童半导体 | | ||
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING DESCRIPTION The 74LVQ373 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. These 8 bit D-Type latch are controlled by a latc | STMICROELECTRONICS 意法半导体 | | ||
LOW VOLTAGE CMOS OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING 文件：289.17 Kbytes Page：13 Pages | STMICROELECTRONICS 意法半导体 | | ||
OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT NON INVERTING | STMICROELECTRONICS 意法半导体 | | ||
LOW VOLTAGE CMOS OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING 文件：289.17 Kbytes Page：13 Pages | STMICROELECTRONICS 意法半导体 | | ||
封装/外壳：20-LSSOP（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC LATCH TRANSP OCT 3ST 20QSOP 集成电路（IC） 锁存器 | ONSEMI 安森美半导体 | | ||
封装/外壳：20-LSSOP（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC LATCH TRANSP OCT 3ST 20QSOP 集成电路（IC） 锁存器 | ONSEMI 安森美半导体 | | ||
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING | STMICROELECTRONICS 意法半导体 | | ||
LOW VOLTAGE CMOS OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING 文件：289.17 Kbytes Page：13 Pages | STMICROELECTRONICS 意法半导体 | |
74LVQ373产品属性
- 类型
描述
- 型号
74LVQ373
- 功能描述
闭锁 Octal D Latch
- RoHS
否
- 制造商
Micrel
- 电路数量
1
- 逻辑类型
CMOS
- 逻辑系列
TTL
- 极性
Non-Inverting
- 输出线路数量
9
- 电源电压-最大
12 V
- 电源电压-最小
5 V
- 最大工作温度
+ 85 C
- 最小工作温度
- 40 C
- 封装/箱体
SOIC-16
- 封装
Reel
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
onsemi(安森美) |
24+ |
QSOP20 |
945 |
只做原装,提供一站式配单服务,代工代料。BOM配单 |
|||
ST/意法 |
24+ |
NA/ |
1710 |
优势代理渠道,原装正品,可全系列订货开增值税票 |
|||
ST |
24+ |
TSSOP |
80000 |
只做自己库存 全新原装进口正品假一赔百 可开13%增 |
|||
ST |
25+ |
SOP |
16900 |
原装，请咨询 |
|||
ST |
24+ |
SOP-20 |
2500 |
只做原装正品现货 欢迎来电查询15919825718 |
|||
原厂 |
25+ |
728 |
百分百原装正品 真实公司现货库存 本公司只做原装 可 |
||||
ST/意法 |
2223+ |
TSSOP |
26800 |
只做原装正品假一赔十为客户做到零风险 |
|||
ST |
06+ |
?SSOP-20 |
1000 |
自己公司全新库存绝对有货 |
|||
STMicroelectronics |
25+ |
20-TSSOP(0.173 4.40mm 宽) |
9350 |
独立分销商 公司只做原装 诚心经营 免费试样正品保证 |
|||
ON/安森美 |
25+ |
电联咨询 |
7800 |
公司现货,提供拆样技术支持 |
74LVQ373芯片相关品牌
74LVQ373规格书下载地址
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74LVQ373数据表相关新闻
74LVT374PW
74LVT374PW
2023-5-1974LVT16245BDGGRE4
74LVT16245BDGGRE4
2023-5-1974LVT16245BBX+518
74LVT16245BBX+518
2023-5-1974LVCH16244ADGG-QJ
74LVCH16244ADGG-QJ
2023-5-1974LVCH162245
PDIP-20 总线收发器 , SO-20 + 125 C 总线收发器 , 74VHCT 总线收发器 , 2 V 总线收发器 , SOIC-20 总线收发器 , LQFP-100 总线收发器
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74LVQ11是一个低电压CMOS三重3输入与门亚微米制造硅栅和双层金属布线C2MOS技术。它是理想的低功耗和低噪音3.3V应用。 内部电路是由3个阶段包括缓冲输出，从而使高噪声免疫力和稳定的输出。 所有输入和输出都配备了防止静电放电保护电路，让他们2KV的静电放电抗扰度和瞬态过剩电压。 高速：TPD =4.7ns（典型值）VCC= 3.3 V 兼容TTL输出 低功耗：ICC=2毫安（最大值）在TA= 25℃ 低噪声：VOLP=0.3V VCC= 3.3V（典型值） 75W的传输线路驱动 CAPA
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DdatasheetPDF页码索引
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