General Description

The LVQ373 consists of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state.

Features

■ Ideal for low power/low noise 3.3V applications

■ Implements patented EMI reduction circuitry

■ Available in SOIC JEDEC, SOIC EIAJ and QSOP packages

■ Guaranteed simultaneous switching noise level and

dynamic threshold performance

■ Improved latch-up immunity

■ Guaranteed incident wave switching into 75Ω

■ 4 kV minimum ESD immunity