| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc | Philips 飞利浦 |   | ||
Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J | NEXPERIA 安世 | | ||
Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc | Philips 飞利浦 | | ||
Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc | Philips 飞利浦 | | ||
Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J | NEXPERIA 安世 | | ||
Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc | Philips 飞利浦 | |
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
PHI |
24+ |
NA/ |
14337 |
原装现货,当天可交货,原型号开票 |
|||
PHI |
24+ |
SOP14 |
20000 |
全新原厂原装，进口正品现货，正规渠道可含税！！ |
|||
HARRIS/哈里斯 |
25+ |
IC |
880000 |
明嘉莱只做原装正品现货 |
|||
24+ |
5000 |
公司存货 |
|||||
恩XP |
18+ |
DIP14 |
85600 |
保证进口原装可开17%增值税发票 |
|||
PHI |
25+ |
封装 |
500000 |
源自原厂成本,高价回收工厂呆滞 |
|||
恩XP |
1922+ |
NA |
9200 |
公司原装现货假一罚十特价欢迎来电咨询 |
|||
恩XP |
24+ |
N/A |
25843 |
公司原厂原装现货假一罚十!特价出售!强势库存! |
|||
恩XP |
24+ |
SOP |
4800 |
原装现货,可开13%税票 |
|||
恩XP |
24+ |
N/A |
6540 |
原装现货/欢迎来电咨询 |
74HCT107P规格书下载地址
74HCT107P参数引脚图相关
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- 74HC75N
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2020-10-16
DdatasheetPDF页码索引
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