Quad Two-Input NAND Buffer

General Description This device contains four independent gates, each of which performs the logic NAND function.

Quad 2-input NAND buffer

Quad 2-input NAND buffer

Quad 2-input NAND buffer

Quad Two-Input NAND Buffer

Latch/flip-flop

FEATURES • 8-bit transparent latch — 74F373 • 8-bit positive edge triggered register — 74F374 • 3-State outputs glitch free during power-up and power-down • Common 3-State output register • Independent register and 3-State buffer operation • SSOP Type II Package DESCRIPTION The 74F373 is a

Octal transparent latch 3-State

DESCRIPTION The 74F373 is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates. The data on the D inputs is transferred to the latch outputs when the enable (E) input is

Octal Transparent Latch with 3-STATE Outputs

General Description The 74F373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Outpu

74F373 Octal Transparent Latch with 3-STATE Outputs

General Description The 74F373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Outpu

Octal Transparent Latch with 3-STATE Outputs

General Description The 74F373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Outpu

Octal Transparent Latch with 3-STATE Outputs

General Description The 74F373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Outpu

74F373 Octal Transparent Latch with 3-STATE Outputs

General Description The 74F373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Outpu

74F373 Octal Transparent Latch with 3-STATE Outputs

General Description The 74F373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Outpu

Octal Transparent Latch with 3-STATE Outputs

General Description The 74F373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Outpu

74F373 Octal Transparent Latch with 3-STATE Outputs

General Description The 74F373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Outpu

74F373 Octal Transparent Latch with 3-STATE Outputs

General Description The 74F373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Outpu

Octal Transparent Latch with 3-STATE Outputs

General Description The 74F373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Outpu

Octal D-Type Flip-Flop with 3-STATE Outputs

General Description The 74F374 is a high-speed, low-power octal D-type flipflop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flipflops. Features ■ Edge-triggered D-type input

Octal transparent latch 3-State

DESCRIPTION The 74F373 is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates. The data on the D inputs is transferred to the latch outputs when the enable (E) input is

Latch/flip-flop

FEATURES • 8-bit transparent latch — 74F373 • 8-bit positive edge triggered register — 74F374 • 3-State outputs glitch free during power-up and power-down • Common 3-State output register • Independent register and 3-State buffer operation • SSOP Type II Package DESCRIPTION The 74F373 is a

Octal D-Type Flip-Flop with 3-STATE Outputs

General Description The 74F374 is a high-speed, low-power octal D-type flipflop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flipflops. Features ■ Edge-triggered D-type input

Octal D-Type Flip-Flop with 3-STATE Outputs

General Description The 74F374 is a high-speed, low-power octal D-type flipflop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flipflops. Features ■ Edge-triggered D-type input

Octal D-Type Flip-Flop with 3-STATE Outputs

General Description The 74F374 is a high-speed, low-power octal D-type flipflop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flipflops. Features ■ Edge-triggered D-type input

Octal D-Type Flip-Flop with 3-STATE Outputs

General Description The 74F374 is a high-speed, low-power octal D-type flipflop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flipflops. Features ■ Edge-triggered D-type input

Octal D-Type Flip-Flop with Clock Enable

General Description The 74F377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one set

Octal D-type flip-flop with enable

DESCRIPTION The 74F377A has 8 edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low. The register is fully edge triggered. The state of each D input, one set-up time befor

Octal D-Type Flip-Flop with Clock Enable

General Description The 74F377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one set

Octal D-Type Flip-Flop with Clock Enable

General Description The 74F377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one set

Octal D-Type Flip-Flop with Clock Enable

General Description The 74F377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one set

Parallel D-Type Register with Enable

General Description The 74F378 is a 6-bit register with a buffered common Enable. This device is similar to the 74F174, but with common Enable rather than common Master Reset. Features ■ 6-bit high-speed parallel register ■ Positive edge-triggered D-type inputs ■ Fully buffered common clock

Hex D flip-flop with enable

DESCRIPTION The 74F378 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low. The register is fully edge-triggered. The state of each D input, one setup time befor

Parallel D-Type Register with Enable

General Description The 74F378 is a 6-bit register with a buffered common Enable. This device is similar to the 74F174, but with common Enable rather than common Master Reset. Features ■ 6-bit high-speed parallel register ■ Positive edge-triggered D-type inputs ■ Fully buffered common clock

Parallel D-Type Register with Enable

General Description The 74F378 is a 6-bit register with a buffered common Enable. This device is similar to the 74F174, but with common Enable rather than common Master Reset. Features ■ 6-bit high-speed parallel register ■ Positive edge-triggered D-type inputs ■ Fully buffered common clock

Parallel D-Type Register with Enable

General Description The 74F378 is a 6-bit register with a buffered common Enable. This device is similar to the 74F174, but with common Enable rather than common Master Reset. Features ■ 6-bit high-speed parallel register ■ Positive edge-triggered D-type inputs ■ Fully buffered common clock

Quad Parallel Register with Enable

General Description The 74F379 is a 4-bit register with buffered common Enable. This device is similar to the 74F175 but features the common Enable rather than common Master Reset. Features ■ Edge triggered D-type inputs ■ Buffered positive edge-triggered clock ■ Buffered common enable input

Quad register

DESCRIPTION The 74F379A is a 4–bit register with buffered common enable (E). This device is similar to the 74F175A but features the common enable rather than common master reset. FEATURES • Edge–triggered D–type inputs • Buffered positive edge–triggered clock • Buffered common enable input •

Quad Parallel Register with Enable

General Description The 74F379 is a 4-bit register with buffered common Enable. This device is similar to the 74F175 but features the common Enable rather than common Master Reset. Features ■ Edge triggered D-type inputs ■ Buffered positive edge-triggered clock ■ Buffered common enable input

Quad Parallel Register with Enable

General Description The 74F379 is a 4-bit register with buffered common Enable. This device is similar to the 74F175 but features the common Enable rather than common Master Reset. Features ■ Edge triggered D-type inputs ■ Buffered positive edge-triggered clock ■ Buffered common enable input

Quad Parallel Register with Enable

General Description The 74F379 is a 4-bit register with buffered common Enable. This device is similar to the 74F175 but features the common Enable rather than common Master Reset. Features ■ Edge triggered D-type inputs ■ Buffered positive edge-triggered clock ■ Buffered common enable input

Quad Two-Input NAND Buffer

General Description This device contains four independent gates, each of which performs the logic NAND function.

Quad Two-Input NAND Buffer

General Description This device contains four independent gates, each of which performs the logic NAND function.

Quad Two-Input NAND Buffer

General Description This device contains four independent gates, each of which performs the logic NAND function.

Octal Transparent Latch with TRI-STATE Outputs

文件：174.64 Kbytes Page：8 Pages

Octal transparent latch (3-State), Octal D flip-flop (3-State)

Octal Transparent Latch with TRI-STATE Outputs

文件：174.64 Kbytes Page：8 Pages

封装/外壳：20-SSOP（0.209"，5.30mm 宽） 包装：卷带（TR） 描述：IC LATCH TRANSP OCT 3ST 20SSOP 集成电路（IC） 锁存器

Octal Transparent Latch with TRI-STATE Outputs

文件：174.64 Kbytes Page：8 Pages

封装/外壳：20-DIP（0.300"，7.62mm） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC LATCH TRANSPARENT OCT 20-DIP 集成电路（IC） 锁存器

Octal Transparent Latch with TRI-STATE Outputs

文件：174.64 Kbytes Page：8 Pages

Octal Transparent Latch with TRI-STATE Outputs

文件：174.64 Kbytes Page：8 Pages

Octal D-Type Flip-Flop with 3-STATE Outputs

文件：80.59 Kbytes Page：8 Pages

Octal D-Type Flip-Flop with 3-STATE Outputs

文件：80.59 Kbytes Page：8 Pages

Octal D-Type Flip-Flop with TRI-STATE Outputs

文件：175.92 Kbytes Page：8 Pages

Octal D-Type Flip-Flop with TRI-STATE Outputs

文件：175.92 Kbytes Page：8 Pages

Octal D-Type Flip-Flop with 3-STATE Outputs

文件：80.59 Kbytes Page：8 Pages

Octal D-Type Flip-Flop with TRI-STATE Outputs

文件：175.92 Kbytes Page：8 Pages

Octal D-Type Flip-Flop with 3-STATE Outputs

文件：80.59 Kbytes Page：8 Pages

Octal D-Type Flip-Flop with TRI-STATE Outputs

文件：175.92 Kbytes Page：8 Pages

Octal D-Type Flip-Flop with 3-STATE Outputs

文件：80.59 Kbytes Page：8 Pages

Octal D-Type Flip-Flop with Clock Enable

文件：75.98 Kbytes Page：7 Pages

Octal D-Type Flip-Flop with Clock Enable

文件：75.98 Kbytes Page：7 Pages