Octal Transparent Latch with 3-STATE Outputs

General Description The 74F373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Outpu

74F373 Octal Transparent Latch with 3-STATE Outputs

General Description The 74F373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Outpu

封装/外壳：20-SSOP（0.209"，5.30mm 宽） 包装：卷带（TR） 描述：IC LATCH TRANSP OCT 3ST 20SSOP 集成电路（IC） 锁存器

Octal Transparent Latch with TRI-STATE Outputs

文件：174.64 Kbytes Page：8 Pages

Octal Transparent Latch with 3-STATE Outputs

General Description The 74F373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Outpu

Latch/flip-flop

FEATURES • 8-bit transparent latch — 74F373 • 8-bit positive edge triggered register — 74F374 • 3-State outputs glitch free during power-up and power-down • Common 3-State output register • Independent register and 3-State buffer operation • SSOP Type II Package DESCRIPTION The 74F373 is a

Octal transparent latch 3-State

DESCRIPTION The 74F373 is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates. The data on the D inputs is transferred to the latch outputs when the enable (E) input is

Octal Transparent Latch with TRI-STATE Outputs

文件：174.64 Kbytes Page：8 Pages

封装/外壳：20-SSOP（0.209"，5.30mm 宽） 包装：卷带（TR） 描述：IC LATCH TRANSP OCT 3ST 20SSOP 集成电路（IC） 锁存器