Parallel D-Type Register with Enable

General Description The 74F378 is a 6-bit register with a buffered common Enable. This device is similar to the 74F174, but with common Enable rather than common Master Reset. Features ■ 6-bit high-speed parallel register ■ Positive edge-triggered D-type inputs ■ Fully buffered common clock

Hex D flip-flop with enable

DESCRIPTION The 74F378 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low. The register is fully edge-triggered. The state of each D input, one setup time befor

Hex D flip-flop with enable

Parallel D-Type Register with Enable

General Description\nThe 74F378 is a 6-bit register with a buffered common Enable. This device is similar to the 74F174, but with common Enable rather than common Master Reset. ■ 6-bit high-speed parallel register\n■ Positive edge-triggered D-type inputs\n■ Fully buffered common clock and enable inputs\n■ Input clamp diodes limit high-speed termination effects\n■ Full TTL and CMOS compatible;

Parallel D-Type Register with Enable

General Description The 74F378 is a 6-bit register with a buffered common Enable. This device is similar to the 74F174, but with common Enable rather than common Master Reset. Features ■ 6-bit high-speed parallel register ■ Positive edge-triggered D-type inputs ■ Fully buffered common clock

Parallel D-Type Register with Enable

General Description The 74F378 is a 6-bit register with a buffered common Enable. This device is similar to the 74F174, but with common Enable rather than common Master Reset. Features ■ 6-bit high-speed parallel register ■ Positive edge-triggered D-type inputs ■ Fully buffered common clock

Parallel D-Type Register with Enable

General Description The 74F378 is a 6-bit register with a buffered common Enable. This device is similar to the 74F174, but with common Enable rather than common Master Reset. Features ■ 6-bit high-speed parallel register ■ Positive edge-triggered D-type inputs ■ Fully buffered common clock

Parallel D Register with Enable

文件：166.93 Kbytes Page：8 Pages

封装/外壳：16-DIP（0.300"，7.62mm） 功能：标准 包装：袋 描述：IC FF D-TYPE SNGL 6BIT 16DIP 集成电路（IC） 触发器

Parallel D Register with Enable

文件：166.93 Kbytes Page：8 Pages

Parallel D Register with Enable

文件：166.93 Kbytes Page：8 Pages

Hex D flip-flop with enable

DESCRIPTION The 74F378 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low. The register is fully edge-triggered. The state of each D input, one setup time befor

Hex D flip-flop with enable

DESCRIPTION The 74F378 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low. The register is fully edge-triggered. The state of each D input, one setup time befor