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71V65703价格

参考价格:¥94.7400

型号:71V65703S85BQ 品牌:IDT 备注:这里有71V65703多少钱,2026年最近7天走势,今日出价,今日竞价,71V65703批发/采购报价,71V65703行情走势销售排行榜,71V65703报价。
型号 功能描述 生产厂家 企业 LOGO 操作
71V65703

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

71V65703

3.3V 256K x 36 ZBT Synchronous 3.3V I/O Flowthrough SRAM

The 71V65703 3.3V CMOS SRAM is organized as 256K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65703 contain address, data-in and control signal regist High performance system speed - 100 MHz\n(7.5 ns Clock-to-Data Access)\nZBTTM Feature - No dead cycles between write and read\ncycles\nInternally synchronized output buffer enable eliminates the need to control OE\nSingle R/W (READ/WRITE) control pin\n4-word burst capability (Interleaved or linear)\;

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/

RENESAS

瑞萨

封装/外壳:119-BGA 包装:托盘 描述:IC SRAM 9MBIT PARALLEL 119PBGA 集成电路(IC) 存储器

RENESAS

瑞萨

封装/外壳:119-BGA 包装:卷带(TR) 描述:IC SRAM 9MBIT PARALLEL 119PBGA 集成电路(IC) 存储器

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs

文件:504.78 Kbytes Page:26 Pages

IDT

3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

文件:615.34 Kbytes Page:23 Pages

IDT

更新时间:2026-5-24 22:14:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
IDT
26+
BGA
20000
公司只有正品,实单来谈
IDT
2026+
BGA
996880
只做原装 欢迎来电资询
IDT, Integrated Device Technol
24+25+
16500
全新原厂原装现货!受权代理!可送样可提供技术支持!
IDT
24+
QFP
67
IDT
25+
NA
9000
只做原装正品 有挂有货 假一赔十
IDT
24+
N
5000
全新原装正品,现货销售
IDT
16+
QFP
4000
进口原装现货/价格优势!
RENESAS(瑞萨)/IDT
2447
PBGA-119(14x22)
315000
84个/托盘一级代理专营品牌!原装正品,优势现货,长
IDT
25+
N
8000
只有原装
IDT
23+
BGA
5107
所有报价以当天为准

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