DDR TERMINATION REGULATOR

DESCRIPTION The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic) specifications for termination of DDR-SDRAM. It also can be used in SSTL-3 or HSTL (High-Speed Transceiver Logic) scheme. The device contains a high-speed OP AMP to pro

DDR TERMINATION REGULATOR

DESCRIPTION The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic) specifications for termination of DDR-SDRAM. It also can be used in SSTL-3 or HSTL (High-Speed Transceiver Logic) scheme. The device contains a high-speed OP AMP to pro

100 MHz to 40 GHz Linear-in-dB RMS Power Detector with 35 dB Dynamic Range

FEATURES ► Ultra-wide matched input frequency range: 100 MHz to 40 GHz ► 35 dB linear dynamic range (

100 MHz to 40 GHz Linear-in-dB RMS Power Detector with 35 dB Dynamic Range

FEATURES ► Ultra-wide matched input frequency range: 100 MHz to 40 GHz ► 35 dB linear dynamic range (

100MHz to 70GHz Linear-in-dB RMS Power Detector with 35dB Dynamic Range

文件：2.2276 Mbytes Page：22 Pages

100MHz to 40GHz Linear-in-dB RMS Power Detector with 35dB Dynamic Range

文件：2.3483 Mbytes Page：22 Pages

Street Fire HEI Module

文件：222 Kbytes Page：2 Pages