Features

● TC358860XBG follows the following standards:

 MIPI Alliance Specification for Display Serial

Interface (DSI) version 1.1, Nov 22 2011

 MIPI Alliance Specification for D-PHY Version

1.1, Nov 7 2011

 VESA DisplayPort Standard version 1.2a, May

23 2012.

 VESA Embedded DisplayPort Standard version

1.4 Feb. 28 2013

● eDP Sink (Receiver)

 Bit Rate @ 1.62, 2.16, 2.7, 3.24, 4.32 or

5.4Gbps, Voltage Swing @0.2 to 1.2 V, Pre-

Emphasis Level @3.5dB.

 There are four lanes available in eDP main Link,

which can operate in 1-, 2- or 4-lane

configuration.

 Support Single-Stream Transport (SST), not

multi-Stream Transport (MST)

 Capable of Full and Fast Link Training

 AUX channel with nominal bit rate at 1 Mbps.

 Video input data formats supported: RGB666

and RGB888

 Absolute maximum pixel rate is 600 Mpixel/s.

 Support Alternate Scrambler Seed Reset

(ASSR) is used for content protection, Does not

support HDCP encryption.

- System designer can connect ASSR_Disable

Pad to GND, which prevents eDPTx (Source

device) to disable ASSR mode TC358860XBG.

- In order words, when ASSR_Disable Pad is

grounded, the Source device cannot clear the

ALTERNATE_SCRAMBER_RESET_ENABLE

bit of the eDP_CONFIGURATION_SET register

(DPCD Address 0010Ah, bit 0) to 0.

 No audio SDP, Multi-touch and Backlight DPCD

registers support

 Support REFCLK from 24 , 25, 26 and 27MHz.

● DSI Transmitter

 Dual 4-Data Lane DSI Links with Bi-direction

support at Data Lane 0. Each link can be used in

1-, 2-, 3- or 4-data lane configuration. Maximum

speed at 1.0 Gbps/lane.

 No deep color support, Video input data formats:

RGB666 and RGB888

- TC358860XBG performs dithering for RGB888

video stream to RGB666 panel

- TC358860XBG appends MSB bits of RGB666

video stream (RGB[5:0]  {RGB[5:0],

RGB[5:4]) to RGB888 panel

 Interlaced video mode is not supported.

 Dual links with Left-Right split: DSI0 carries the

left half data of eDP Rx video stream and DSI1

carries the right one

- DSI0 can be assigned/programmed to either

DSITx port.

- The maximum length of each half is limited to

2048-pixel plus up to 32-pixel overlap.

- The skew (DSI1 delay w.r.t. to DSI0) between

DSI0 and DSI1 can be programmed by register

 Provide path for eDP host/transmitter to control

TC358860XBG and its attached panel.

 Built in Color Bar Generator to verify Dual DSI

link without eDPRx input.

 DSITx operates in video mode when video

stream is continuously received at eDPRx port.

● Video function

 Compression engine : 2 to 1 compression for

4k2k resolution

 Magic square

 Color bar output for debug

● I2C Slave Port

 Support for normal (100 kHz), fast (400 kHz or 1

MHz, if SysClk is running at 25 MHz) modes.

 External I2C master can access TC358860XBG

internal and DPCD registers and read/write DSI

panel register (via DSI link).

 Address auto increment is supported.

 TC358860XBG Slave Port address is 0x68,

(binary 1101_000x) where x = 1 for read and x =

0 for write. The slave address can be changed to

0x0E (binary 0001_110x) by a weak pull up to

pin GPIO0 during boot time.

● Power Supply

 MIPI D-PHY 1.2 V

 Core, MIPI D-PHY and eDP-PHY 1.1 V

 eDP-PHY: 1.8 V

 I/O: 1.8 V or 3.3 V (all IO pins

must be same power level)

 HPD Output Pad 1.8 V or 3.3 V

● Power Consumption (Typical Condition)

 126 mW

- Condition: Input 5.4 Gbps eDP 1 lane, Output

DSI port 4 data lane, Full HD@60fps resolution,

24 bpp

● Packaging

 65-pin FBGA Package with 0.5 mm ball pitch

 5 x 5 mm2