Features

● TC358770AXBG / TC358777XBG follows the

following standards:

 MIPI® DSISM version 1.02, Jan 2010.

 MIPI® D-PHYSM version 1.0, May 2009.

 VESA® DisplayPortTM Standard version 1.1a,

Jan. 11 2008.

 Digital Content Protection LLC, HDCP version

1.3 with DisplayPortTM amendment revision 1.1,

Jan. 15 2010.

● DSI Receiver

 Dual 4-Data Lane DSI Link with Bi-direction

support at Data Lane 0, it can be used in 1-, 2-,

3- or 4-data lane configuration.

 Maximum speed at 1 Gbps/lane.

 Video input data formats: RGB-565, RGB-666

and RGB-888.

 New DSI V1.02 Data Type, 16-bit YCbCr 422, is

supported.

 Interlaced video mode is not supported.

 Provide path for DSI host/transmitter to control

TC358770AXBG / TC358777XBG and its

attached panel.

 DSI Link High Speed clock, DSIClk or an

external clock, RefClk, is required before

programming TC358770AXBG.

● DisplayPortTM Source/Transmitter

 VESA® DisplayPortTM Rev 1.1a Standard.

- Bit Rate @ 1.62 or 2.7 Gbps, Voltage Swing

@0.4, 0.6, 0.8 or 1.2 V, Pre-Emphasis Level

@0, 3.5 or 6dB.

- There are four lanes available in DP main Link,

which can operate in 1-, 2- or 4-lane

configuration.

- AUX channel with nominal bit rate at 1 Mbps.

 After receiving DSI link burst data,

TC358770AXBG / TC358777XBG retimes video

data to DP panel's pixel clock for Synchronous

(to DisplayPortTM link symbol clock, LSClk) Clock

Mode operation.

 SSCG with up to 30 kHz modulation to reduce

EMI.

 Built in PRBS7 Generator to test DisplayPortTM

Link without DSI input.

 Built in Color Bar Generator to verify

DisplayPortTM protocol.

 Support HDCP encryption Version 1.3 with

DisplayPortTM amendment Revision 1.1.

 Secure ASSR (Alternate Scrambler Seed Reset)

support for eDP panels

- System designer connects ASSR_DisablePad

to an inner ring VSS_IO pad, e.g. pad E4, to

enable eDP panels and ASSR

- Drive ASSR_DisablePad with an inner ring

VDDS pad, e.g. pad D5, for using DP panels

and disable ASSR

- System software read Revision ID field,

0x0500[7:0]:

 0x01 indicates eDP panels are used, DPCD

register bit 0x0010A[0] of eDP panel should be

set.

 0x03 assumes DP panels are connected,

DPCD register bit 0x0010A[0] of DP panel

should Not be set.

● I2C Slave Port

 Support for normal (100 kHz) and fast (400 kHz)

modes.

 External I2C master can access

TC358770AXBG / TC358777XBG internal

registers via this port.

 Address auto increment is supported.

 TC358770AXBG / TC358777XBG Slave Port

address is 0x68, (binary 1101_000x) where x = 1

for read and x = 0 for write. The slave address

can be changed to 0x0F (binary 0001_111x) by

tying pin SPI_SS/I2C_ADR_SEL to high.

● SPI Slave Interface

 Slave select pin supported.

 Clock Polarity and Phase as per SPI MODE0

(polarity = 0, phase = 0).

 Transfer Frame size of 48 bits.

 Maximum clock speed is up to 30 MHz.

● Audio Interface

 Support either I2S or TDM (Time Division

Multiplex) mode.

 TDM mode can support 2, 4, 6 and 8 channel of

audio data.

 Support 16, 18, 20 or 24-bit PCM audio data

word.

 Sample frequency, fs, supported: 32, 44.1, 48,

88.2, 96, 176.4 & 192 kHz.

 512 * fs audio oversample clock is required to

generate accurate auido clock timestamps in

order for the DisplayPortTM panel to recover

audio clock correctly.

 Ability to insert IEC60958 status bits and

preamble bits per channel.

● Operation

 Host programs TC358770AXBG /

TC358777XBG either by using DSI link 0 (DSI0),

I2C bus or SPI bus.

 TC358770AXBG / TC358777XBG provides

mailbox registers, 20-bit AuxAddr and 16-byte

AuxData, for Host to access DisplayPortTM

Panel's DisplayPortTM Configuration Data,

DPCD, registers.

 Host splits a video line data into two streams of

DSI video packets. Host has two options to split

the video line data:

- Left-Right Side: Left (first) side video packet

goes to DSI0 and Right side data to DSI1.

- Even-Odd Group: Even (first) groups of pixels

are transmitted in DSI0 while Odd ones are

carried by DSI1.

 The number of pixels per group is

programmable; from 1 to 64.

 The number of pixels per group and/or the

number of groups in each video packet can be

different between the two DSI links. This

feature in connection with TC358770AXBG's

capability to support configurable number of

data lanes.

- It is recommended that host pack the split video

line data into one video packet for each DSI link

before transmitting. However, TC358770AXBG /

TC358777XBG supports multiple DSI packets

per horizontal line time as long as DSI link

bandwidth is enough for the overhead.

 TC358770AXBG / TC358777XBG is responsible

to generate video frame timing based on the

register values set by the Host. Host does not

have to care/generate video horizontal timings,

such as Horizontal Front/Back Porch and

Horizontal Pulse width. Host is responsible to

send the video data packets to TC358770AXBG

/ TC358777XBG in time line-by-line and

separated each line data by HSS.

- Host is expected to send exactly one line of

video data per horizontal sync period between

the two DSI links.

- Host is expected to start HSS0, HSS packet of

DSI0, and HSS1, HSS packet of DSI1, either at

the same time or with fixed delay/skew

between them (HSS0 earlier than that of HSS1).

 The same time means within +/- 5 clock

cycles.

- The time skew between the two DSI links'

Hsync Start, HSS, packet cannot drift more

than one video line time within one video frame

period.

 Host is recommended to use the same clock

source to generate both DSI link clocks in

order to prevent these two clocks from drifting

away.

 Otherwise, clock sources with 50 ppm

accuracy are required.

- It is recommended that each DSI link sends

HSS and video packets back-to-back. Host can

insert variable length of blanking packet

between HSS and video packets as long as the

bandwidth is allowed.

 TC358770AXBG / TC358777XBG concatenates

two (streams of) video packets, one (stream)

from each DSI link, into a single DisplayPortTM

video stream before transmitting it out to the

panel.

● Clock Source:

 An external reference clock, RefClk, is used to

drive PLLs for generating DisplayPort's

stream/pixel clock, StrmClk/PixelClk, and Link

Symbol Clock, LSClk.

- Support DisplayPortTM Synchronous (StrmClk

and LSClk) Clock Mode.

- Allowed RefClk Frequency Value: 13, 19.2, 26,

38.4 MHz.

 Optionally, DSI DSIClk can be used/divided

down to replace RefClk and drive PLLs used to

generate the required clocks.

- The divisor, from DSI ByteClk, can be either

 3 (115.2 ÷ 3 = 38.4)

 4 (104 ÷ 4 = 26)

 5 (96 ÷ 5 = 19.2)

 9 (117 ÷ 9 = 13)

● Power Supply

 MIPI D-PHY and DP PHY: 1.2 V

 Core: 1.2 V

 DP-PHY: 1.8 V

 I/O: 1.8 V to 3.3 V (all IO pins

must be same power level)

 HPD Input Pad 3.3 V

● Power Consumption (Typical Condition)

 Sleep State, with RESX asserted

- 12 mW

 Typical Operation:

- 2560 × 1440 × 24@60fps

- Dual DSIRx, each link @3.7 Gbps

 31 mW for both Links

- Core

 165 mW

- DP Tx (2.7 Gbps Link speed @4 lanes, 0.4 V

Swing without Pre-Emphasis)

 168.5 mW

- Total = 364.5 mW