Features

● Standard followed:

 MIPI DSI version 1.01, Feb 2008

 MIPI D-PHY version 0.9, Oct 2007

 MIPI DPI version 2.0, Sep, 2005

 MIPI DBI-2 version 2.00, Nov 2005

 MIPI DCS Command version 1.02, Dec 2008

● DSI Receiver

 Dual Data Lane DSI Link with Bi-direction

support at Data Lane 0

 Maximum speed at 800 Mbps/lane

 Video input data formats: RGB-565, RGB-666

and RGB-888

 Video input frame rates: Up to 60 fps for

WXGA (1366 × 768)

 Support various DSI packet types

 Provide the path for DSI host/transmitter to

control TC358762XBG and its attached Display

Device

● DPI Host

 Bus speed up to 75 MHz burst rate with data

rate up to 216 Mbytes/s

 Support the following pixel formats:

- RGB666 18 bit per pixel

- RGB666 loosely packed 18 bit per pixel

- RGB565 16 bit per pixel

- RGB565 loosely packed 16 bit per pixel

- RGB888 24 bit per pixel

 With the Toshiba Magic Square algorithm,

an RGB666 18-bit or 16-bit LCD panel can

produce a display equivalent to that of an

RGB888 24-bit LCD panel with up to 16-

million colors

 Programmable output polarity

 Support up to frame size 1366 × 768 at 60 fps

● DBI Host

 Read/Write Data/Command from the external

DBI slave device

 Support DCS commands, which is compliant

with MIPI DBI-B standard

 Support Intel 80xx CPU I/F with either 8-bit or

16-bit commands

 Programmable Output Data Format and Bus

Width

- 8 bit Bus, RGB 565 (2 cycles/pixel)

- 8 bit Bus, RGB 666 (3 cycles/pixel)

- 8 bit Bus, RGB 888 (3 cycles/pixel)

- 9 bit Bus, RGB 666 (2 cycles/pixel)

- 16 bit Bus, RGB 565 (1 cycles/pixel)

- 16 bit Bus, RGB 666 (3 cycles/2 pixel) note1

- 16 bit Bus, RGB 888 (3 cycles/2 pixel) note1

- 18 bit Bus, RGB 666 (1 cycles/pixel)

- 24 bit Bus, RGB 888 (1 cycles/pixel)

 Support up to 864×480 at 60 fps (or

1280×720 at 30 fps)

SPI Master

 4-pin SPI master I/F, CSX[1:0], CLK, DI and DO

 Support two SPI slaves

 Data Rate up to 10 Mbps

 The main purpose of this port is used to

configure DPI slave display devices

 Half Duplex data transfer support

● DBI-C host

 3-pin DBI-C host I/F, CSX, SCL and SDA

 Shared pins with SPI I/F, only one can be active

at a given time

 Data Rate up to 10 Mbps

 Programmable read delay

● I2C compliant interface Slave Port

 Data Rate up to 400 kHz

 External I2C master can access TC358762XBG

internal registers via this port

 Address auto increment is supported

 TC358762XBG Slave Port address is “0001011”

 During I2C slave cycle, DSI host must not

transmit any new DSI packet to TC358762XBG.

● A 1024 × 24 dual port Video Buffer is used to

buffer the video data received from DSI link.

● System Operation

 Register programming through DSI link via

Generic Write Long packets.

 Register read through DSI link via Generic

Read, 2 parameters packets.

 Write to WCMQUE and RCMDQUE registers

enable host to configure and control peripheral

display device

 DCS commands are routed to peripheral display

device to interpret

 Provide Tearing Effect Trigger message after

receiving set_tear_on command

● Clock source:

 External reference clock: recommended 6 - 40

MHz

 A programmable PLL is used to adjust the

output video clock:

- In DPI output mode with DSI link burst data,

adjust output clock to the desired pixel clock

frequency to assure no video is lost due to

video buffer over/under flow.

- In DBI output mode, adjust output clock

frequency fast enough to prevent video buffer

from over flow.

● Power supply

 MIPI D-PHY: 1.2V

 I/O: 1.8V – 3.3V (all IO pins must be

same power level)

 Core: 1.2V

● Power Consumption

 Sleep State

- PLL OFF mode - Sleep mode (DSI-CLK stops

toggle)

 IOs: 0.05 μW

 CORE: 23 μW

 D-PHYs: 3 mW

 PLLs: Off (PLL power – 0V)

- PLL ON mode - Sleep mode (DSI-CLK goes

to ULPS state, REFCLK toggles)

 IOs: 0.15 μW

 CORE: 23 μW

 D-PHYs: 9 μW

 PLLs: 28 μW

 Normal Operation:

- PLLOFF mode (480×864 @60fps, DSI-CLK:

400 MHz – 2 data lanes)

 18 mW

 PLLON mode (480×864 @60fps, DSI-CLK:

400 MHz, PLLCLK: 50.28MHz, PCLK=PLL/2)

 19 mW

● Packaging

 BGA 64 pins

 5.0mm × 5.0mm × 1mm

 0.5mm ball pitch