Members of the Texas Instruments (TIE)

Broad Family of Testability Products

Supporting IEEE Std 1149.1-1990 (JTAG)

Test Access Port (TAP) and Boundary-Scan

Architecture

Extend Scan Access From Board Level to

Higher Levels of System Integration

Promote Reuse of Lower-Level

Chip/Board) Tests in System Environment

While Powered at 3.3 V, Both the Primary

and Secondary TAPs Are Fully 5-V Tolerant

for Interfacing to 5-V and/or 3.3-V Masters

and Targets

Switch-Based Architecture Allows Direct

Connect of Primary TAP to Secondary TAP

Primary TAP Is Multidrop for Minimal Use of

Backplane Wiring Channels

Shadow Protocols Can Occur in Any of

Test-Logic-Reset, Run-Test/Idle, Pause-DR,

and Pause-IR TAP States to Provide for

Board-to-Board Test and Built-In Self-Test

Simple Addressing (Shadow) Protocol Is

Received/Acknowledged on Primary TAP

10-Bit Address Space Provides for up to

1021 User-Specified Board Addresses

Bypass (BYP) Pin Forces

Primary-to-Secondary Connection Without

Use of Shadow Protocols

Connect (CON) Pin Provides Indication of

Primary-to-Secondary Connection

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

Support Backplane Interface at Primary and

High Fanout at Secondary

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

Package Options Include Plastic

Small-Outline (DW) and Thin Shrink

Small-Outline (PW) Packages, Ceramic

Chip Carriers (FK), and Ceramic DIPs (JT)