1 Features

1• Up to 6.384-Gbps Throughput

• 66-MHz to 133-MHz Input Clock Support

• Reduces Cable and Connector Size and Cost

• Pre-Emphasis Reduces Cable Loading Effects

• DC Balance Reduces ISI Distortion

• 24-Bit Double Edge Inputs

• 3-V Tolerant LVCMOS/LVTTL Inputs

• Low Power, 2.5-V Supply

• Flow-Through Pinout

• 100-Pin TQFP Package

• Conforms With TIA/EIA-644-A LVDS Standard

2 Applications

• Backplane

• Cable Interconnect

3 Description

The DS90CR485 device serializes the 24

LVCMOS/LVTTL double-edge inputs (48 bits data

latched in per clock cycle) onto eight Low Voltage

Differential Signaling (LVDS) streams. A phaselocked

transmit clock is also in parallel with the data

streams over a 9th LVDS link. The reduction of the

wide TTL bus to a few LVDS lines reduces cable and

connector size and cost. The double-edge input

strobes data on both the rising and falling edges of

the clock. This minimizes the pin count required and

simplifies PCB routing between the host chip and the

serializer.

This chip can help resolve EMI and interconnect size

problems for high throughput point-to-point

applications.

The DS90CR485 is compatible with the DS90CR486

Channel-Link receiver. The device is also backwardcompatible

with other Channel-Link receivers such as

the DS90CR482 and DS90CR484.