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DS90CR484VJD/NOPB中文资料
DS90CR484VJD/NOPB数据手册规格书PDF详情
1FEATURES
2• Up to 5.38 Gbits/sec Bandwidth
• 33 MHz to 112 MHz Input Clock Support
• LVDS SER/DES Reduces Cable and connector
Size
• Pre-Emphasis Reduces Cable Loading Effects
• DC Balance Data Transmission Provided by
Transmitter Reduces ISI Distortion
• Cable Deskew of +/−1 LVDS Data Bit Time (up
to 80 MHz Clock Rate)
• 5V Tolerant TxIN and Control Input Pins
• Flow Through Pinout for Easy PCB Design
• +3.3V Supply Voltage
• Transmitter Rejects Cycle-to-Cycle Jitter
• Conforms to ANSI/TIA/EIA-644-1995 LVDS
Standard
• Both Devices are Available in 100 Lead TQFP
Package
DESCRIPTION
The DS90CR483 transmitter converts 48 bits of
CMOS/TTL data into eight LVDS (Low Voltage
Differential Signaling) data streams. A phase-locked
transmit clock is transmitted in parallel with the data
streams over a ninth LVDS link. Every cycle of the
transmit clock 48 bits of input data are sampled and
transmitted. The DS90CR484 receiver converts the
LVDS data streams back into 48 bits of CMOS/TTL
data. At a transmit clock frequency of 112MHz, 48
bits of TTL data are transmitted at a rate of 672Mbps
per LVDS data channel. Using a 112MHz clock, the
data throughput is 5.38Gbit/s (672Mbytes/s).
The multiplexing of data lines provides a substantial
cable reduction. Long distance parallel single-ended
buses typically require a ground wire per active signal
and have very limited noise rejection capability).
Thus, for a 48-bit wide data and one clock, up to 98
conductors are required. With this Channel Link
chipset as few as 19 conductors (8 data pairs, 1 clock pair and a minimum of one ground) are needed. This
provides an 80% reduction in cable width, which
provides a system cost savings, reduces connector
physical size and cost, and reduces shielding
requirements due to the cables' smaller form factor.
The 48 CMOS/TTL inputs can support a variety of
signal combinations. For example, 6 8-bit words or 5
9-bit (byte + parity) and 3 controls.
The DS90CR483/DS90CR484 chipset is improved
over prior generations of Channel Link devices and
offers higher bandwidth support and longer cable
drive with three areas of enhancement. To increase
bandwidth, the maximum clock rate is increased to
112 MHz and 8 serialized LVDS outputs are
provided. Cable drive is enhanced with a user
selectable pre-emphasis feature that provides
additional output current during transitions to
counteract cable loading effects. Optional DC
balancing on a cycle-to-cycle basis, is also provided
to reduce ISI (Inter-Symbol Interference). With preemphasis
and DC balancing, a low distortion eyepattern
is provided at the receiver end of the cable. A
cable deskew capability has been added to deskew
long cables of pair-to-pair skew of up to +/−1 LVDS
data bit time (up to 80 MHz Clock Rate). These three
enhancements allow cables 5+ meters in length to be
driven.
DS90CR484VJD/NOPB产品属性
- 类型
描述
- 型号
DS90CR484VJD/NOPB
- 功能描述
LVDS 接口集成电路
- RoHS
否
- 制造商
Texas Instruments
- 激励器数量
4
- 接收机数量
4
- 数据速率
155.5 Mbps
- 工作电源电压
5 V
- 最大功率耗散
1025 mW
- 最大工作温度
+ 85 C
- 封装/箱体
SOIC-16 Narrow
- 封装
Reel
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
Texas Instruments |
24+ |
100-TQFP(14x14) |
56200 |
一级代理/放心采购 |
|||
TI |
25+ |
QFP-100 |
90 |
就找我吧!--邀您体验愉快问购元件! |
|||
TI/德州仪器 |
24+ |
TQFP-100 |
9600 |
原装现货,优势供应,支持实单! |
|||
TI |
23+ |
N/A |
560 |
原厂原装 |
|||
TI |
22+ |
100TQFP |
9000 |
原厂渠道,现货配单 |
|||
TI/德州仪器 |
25+ |
TQFP100 |
8880 |
原装认准芯泽盛世! |
|||
NSC |
07+36 |
60 |
公司优势库存 热卖中! |
||||
TI/德州仪器 |
23+ |
100-TQFP |
3000 |
一级代理原厂VIP渠道,专注军工、汽车、医疗、工业、 |
|||
TI/德州仪器 |
23+ |
TQFP100 |
9990 |
正规渠道,只有原装! |
|||
TI/德州仪器 |
21+ |
TQFP100 |
9990 |
只有原装 |
DS90CR484VJD/NOPB 价格
参考价格:¥96.5592
DS90CR484VJD/NOPB 资料下载更多...
DS90CR484VJD/NOPB 芯片相关型号
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