1 Features

1• 16-bit resolution, dual-channel, 1-GSPS ADC

• Noise floor: –159 dBFS/Hz

• Spectral performance (fIN = 170 MHz at –1 dBFS):

– SNR: 70 dBFS

– NSD: –157 dBFS/Hz

– SFDR: 86 dBc (including interleaving tones)

– SFDR: 89 dBc (except HD2, HD3, and

interleaving tones)

• Spectral performance (fIN = 350 MHz at –1 dBFS):

– SNR: 67.5 dBFS

– NSD: –154.5 dBFS/Hz

– SFDR: 75 dBc

– SFDR: 85 dBc (except HD2, HD3, and

interleaving tones)

• Channel isolation: 100 dBc at fIN = 170 MHz

• Input full-scale: 1.9 VPP

• Input bandwidth (3 dB): 1.2 GHz

• On-chip dither

• Integrated wideband DDC block

• JESD204B interface with subclass 1 support:

– 2 lanes per ADC at 10.0 Gbps

– 4 lanes per ADC at 5.0 Gbps

– Support for multi-chip synchronization

• Power dissipation: 1.35 W/Ch at 1 GSPS

• Package: 72-pin VQFNP (10 mm × 10 mm)

2 Applications

• Radar and antenna arrays

• Broadband wireless

• Cable CMTS, DOCSIS 3.1 receivers

• Communications test equipment

• Microwave receivers

• Software-defined radio (SDR)

• Digitizers

• Medical imaging and diagnostics

3 Description

The ADS54J60 is a low-power, wide-bandwidth, 16-

bit, 1.0-GSPS, dual-channel, analog-to-digital

converter (ADC). Designed for high signal-to-noise

ratio (SNR), the device delivers a noise floor of

–159 dBFS/Hz for applications aiming for highest

dynamic range over a wide instantaneous bandwidth.

The device supports the JESD204B serial interface

with data rates up to 10 Gbps, supporting two or four

lanes per ADC. The buffered analog input provides

uniform input impedance across a wide frequency

range while minimizing sample-and-hold glitch

energy. Each ADC channel optionally can be

connected to a wideband digital down-converter

(DDC) block. The ADS54J60 provides excellent

spurious-free dynamic range (SFDR) over a large

input frequency range with very low power

consumption.

The JESD204B interface reduces the number of

interface lines, allowing high system integration

density. An internal phase-locked loop (PLL)

multiplies the ADC sampling clock to derive the bit

clock that is used to serialize the 16-bit data from

each channel.