1 Features

1• 16-Bit Resolution, Dual-Channel, 500-MSPS ADC

• Idle Channel Noise Floor: –159 dBFS/Hz

• Spectral Performance (fIN = 170 MHz at –1 dBFS):

– SNR: 73 dBFS

– NSD: –157 dBFS/Hz

– SFDR: 93 dBc

– SFDR: 94 dBc (Except HD2, HD3, and

Interleaving Tone)

• Spectral Performance (fIN = 310 MHz at –1 dBFS):

– SNR: 71.7 dBFS

– NSD: –155.7 dBFS/Hz

– SFDR: 81 dBc

– SFDR: 94 dBc (Except HD2, HD3, and

Interleaving Tone)

• Channel Isolation: 100 dBc at fIN = 170 MHz

• Input Full-Scale: 1.9 VPP

• Input Bandwidth (3 dB): 1.2 GHz

• On-Chip Dither

• Integrated Decimate-by-2 Filter

• JESD204B Interface with Subclass 1 Support:

– 1 Lane per ADC at 10.0 Gbps

– 2 Lanes per ADC at 5.0 Gbps

– Support for Multi-Chip Synchronization

• Power Dissipation: 1.35 W/ch at 500 MSPS

• 72-Pin VQFNP Package (10 mm × 10 mm)

2 Applications

• Radar and Antenna Arrays

• Broadband Wireless

• Cable CMTS, DOCSIS 3.1 Receivers

• Communications Test Equipment

• Microwave Receivers

• Software Defined Radio (SDR)

• Digitizers

• Medical Imaging and Diagnostics

3 Description

The ADS54J69 is a low-power, wide-bandwidth, 16-

bit, 500-MSPS, dual-channel, analog-to-digital

converter (ADC). Designed for high signal-to-noise

ratio (SNR), the device delivers a noise floor of

–159 dBFS/Hz for applications aiming for highest

dynamic range over a wide instantaneous bandwidth.

The device supports the JESD204B serial interface

with data rates up to 10.0 Gbps, supporting one or

two lanes per ADC. The buffered analog input

provides uniform input impedance across a wide

frequency range and minimizes sample-and-hold

glitch energy. Each ADC channel is directly

connected to a wideband digital down-converter

(DDC) block. The ADS54J69 provides excellent

spurious-free dynamic range (SFDR) over a large

input frequency range with very low power

consumption.

The JESD204B interface reduces the number of

interface lines, allowing high system integration

density. An internal phase-locked loop (PLL)

multiplies the ADC sampling clock to derive the bit

clock that is used to serialize the 16-bit data from

each channel.