位置:ADS54J40 > ADS54J40详情

ADS54J40中文资料

厂家型号

ADS54J40

文件大小

4528.96Kbytes

页面数量

84

功能描述

ADS54J42 Dual-Channel, 14-Bit, 625-MSPS, Analog-to-Digital Converter

数据手册

下载地址一下载地址二到原厂下载

生产厂商

TI2

ADS54J40数据手册规格书PDF详情

1 Features

1• 14-Bit Resolution, Dual-Chanel, 625-MSPS ADC

• Noise Floor: –157 dBFS/Hz

• Spectral Performance (fIN = 170 MHz at –1 dBFS):

– SNR: 71.0 dBFS

– NSD: –155.9 dBFS/Hz

– SFDR: 85 dBc

– SFDR: 93 dBc (Except HD2, HD3, and

Interleaving Tones)

• Spectral Performance (fIN = 350 MHz at –1 dBFS):

– SNR: 69 dBFS

– NSD: –153.9 dBFS/Hz

– SFDR: 76 dBc

– SFDR: 90 dBc (Except HD2, HD3, and

Interleaving Tones)

• Channel Isolation: 100 dBc at fIN = 170 MHz

• Input Full-Scale: 1.9 VPP

• Input Bandwidth (3 dB): 1.2 GHz

• On-Chip Dither

• Integrated Wideband DDC Block

• JESD204B Interface with Subclass 1 Support:

– 2 Lanes per ADC at 6.25 Gbps

– 4 Lanes per ADC at 3.125 Gbps

– Support for Multi-Chip Synchronization

• Power Dissipation: 970 mW/Ch at 625 MSPS

• Package: 72-Pin VQFNP (10 mm × 10 mm)

2 Applications

• Radar and Antenna Arrays

• Broadband Wireless

• Cable CMTS, DOCSIS 3.1 Receivers

• Communications Test Equipment

• Microwave Receivers

• Software Defined Radio (SDR)

• Digitizers

• Medical Imaging and Diagnostics

3 Description

The ADS54J42 is a low-power, wide-bandwidth, 14-

bit, 625-MSPS, dual-channel, analog-to-digital

converter (ADC). Designed for high signal-to-noise

ratio (SNR), the device delivers a noise floor of

–157 dBFS/Hz for applications aiming for highest

dynamic range over a wide instantaneous bandwidth.

The device supports the JESD204B serial interface

with data rates up to 6.25 Gbps. The buffered analog

input provides uniform input impedance across a wide

frequency range and minimizes sample-and-hold

glitch energy. Each ADC channel optionally can be

connected to a wideband digital down-converter

(DDC) block. The ADS54J42 provides excellent

spurious-free dynamic range (SFDR) over a large

input frequency range with very low power

consumption.

The JESD204B interface reduces the number of

interface lines, allowing high system integration

density. An internal phase-locked loop (PLL)

multiplies the ADC sampling clock to derive the bit

clock that is used to serialize the 14-bit data from

each channel.

更新时间:2025-12-15 14:46:00
供应商 型号 品牌 批号 封装 库存 备注 价格
TI(德州仪器)
24+
标准封装
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原厂直销,大量现货库存,交期快。价格优,支持账期
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数据转换IC开发工具
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2447
20
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一级代理专营品牌!原装正品,优势现货,长期排单到货
TI
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就找我吧!--邀您体验愉快问购元件!
TI
24+
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TI(德州仪器)
23+
NA
20094
正纳10年以上分销经验原装进口正品做服务做口碑有支持
TI(德州仪器)
24+/25+
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原装正品现货库存价优
TI
23+
N/A
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TI
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25+
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原装认准芯泽盛世!