DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

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CMOS Digital Integrated Circuit Silicon Monolithic Dual J-K Flip-Flop with Preset and Clear

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74HC CMOS logic IC series

CMOS Digital Integrated Circuit Silicon Monolithic Dual J-K Flip-Flop with Preset and Clear

文件：313.61 Kbytes Page：10 Pages

CMOS Digital Integrated Circuit Silicon Monolithic Dual J-K Flip-Flop with Preset and Clear

文件：313.61 Kbytes Page：10 Pages

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：287.67 Kbytes Page：7 Pages

Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)

Dual JK flip-flop with set and reset; positive-edge-trigger

1. General description The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of

High Speed CMOS Logic

Features Output Drive Capability: 10 LSTTL Loads Low Input Current: 1μA Outputs directly interface CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 74LS109.

Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)

High Speed CMOS Logic

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