DUAL J - K FLIP FLOP WITH CLEAR

Dual J-K Flip Flop with Clear The TC74HC107A is a high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. In accordance with the logic levels applied to t

DUAL J - K FLIP FLOP WITH CLEAR

Dual J-K Flip Flop with Clear The TC74HC107A is a high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. In accordance with the logic levels applied to t

DUAL J - K FLIP FLOP WITH CLEAR

Dual J-K Flip Flop with Clear The TC74HC107A is a high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. In accordance with the logic levels applied to t

CMOS Digital Integrated Circuit Silicon Monolithic Dual J-K Flip Flop with Clear

文件：300.72 Kbytes Page：9 Pages

CMOS Digital Integrated Circuit Silicon Monolithic Dual J-K Flip Flop with Clear

文件：300.72 Kbytes Page：9 Pages

CMOS Digital Integrated Circuit Silicon Monolithic Dual J-K Flip Flop with Clear

文件：300.72 Kbytes Page：9 Pages

CMOS Digital Integrated Circuit Silicon Monolithic Dual J-K Flip Flop with Clear

文件：300.72 Kbytes Page：9 Pages

74HC CMOS logic IC series

74HC CMOS logic IC series

CMOS Digital Integrated Circuit Silicon Monolithic Dual J-K Flip-Flop with Preset and Clear

文件：313.61 Kbytes Page：10 Pages

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：287.67 Kbytes Page：7 Pages

CMOS Digital Integrated Circuit Silicon Monolithic Dual J-K Flip-Flop with Preset and Clear

文件：313.61 Kbytes Page：10 Pages

CMOS Digital Integrated Circuit Silicon Monolithic Dual J-K Flip-Flop with Preset and Clear

文件：313.61 Kbytes Page：10 Pages

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：287.67 Kbytes Page：7 Pages

CMOS Digital Integrated Circuit Silicon Monolithic Dual J-K Flip-Flop with Preset and Clear

文件：313.61 Kbytes Page：10 Pages

74HC CMOS logic IC series

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：287.67 Kbytes Page：7 Pages

CMOS Digital Integrated Circuit Silicon Monolithic Triple 3-Input NAND Gate

文件：257.63 Kbytes Page：8 Pages

CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC

文件：237.66 Kbytes Page：6 Pages

CMOS Digital Integrated Circuit Silicon Monolithic Triple 3-Input NAND Gate

文件：257.63 Kbytes Page：8 Pages

CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC

文件：237.66 Kbytes Page：6 Pages

CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC

文件：237.66 Kbytes Page：6 Pages

CMOS Digital Integrated Circuit Silicon Monolithic Triple 3-Input NAND Gate

文件：257.63 Kbytes Page：8 Pages

CMOS Digital Integrated Circuit Silicon Monolithic Triple 3-Input NAND Gate

文件：257.63 Kbytes Page：8 Pages

封装/外壳：14-DIP（0.300"，7.62mm） 包装：管件 描述：IC GATE NAND 3CH 3-INP 14DIP 集成电路（IC） 门和反相器

Triple 3-input NAND gate

1. General description The 74HC10; 74HCT10 is a triple 3-input NAND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • Complies with JEDEC standard JESD7A • Input levels: • For74HC10

Triple 3-input NAND gate

GENERAL DESCRIPTION The 74HC/HCT10 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT10 provide the 3-input NAND function. FEATURES • Output capability: standard • ICC categ

Triple 3-input NAND gate

GENERAL DESCRIPTION The 74HC/HCT10 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT10 provide the 3-input NAND function. FEATURES • Output capability: standard • ICC categ

Triple 3-input NAND gate

1. General description The 74HC10; 74HCT10 is a triple 3-input NAND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • Complies with JEDEC standard JESD7A • Input levels: • For74HC10

Triple 3-input NAND gate

GENERAL DESCRIPTION The 74HC/HCT10 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT10 provide the 3-input NAND function. FEATURES • Output capability: standard • ICC categ