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SY100S838价格
参考价格：￥22.7027
型号：SY100S838LZG 品牌：Micrel 备注：这里有SY100S838多少钱，2026年最近7天走势，今日出价，今日竞价，SY100S838批发/采购报价，SY100S838行情走势销售排行榜，SY100S838报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
SY100S838 | (첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 |   | |
SY100S838 | (첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP 文件：483.53 Kbytes Page：5 Pages | Micrel 麦瑞半导体 | | |
SY100S838 | (÷1, ÷2/3) OR (÷2, ÷4/6) CLOCK GENERATION CHIP | Microchip 微芯科技 | | |
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP 文件：483.53 Kbytes Page：5 Pages | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP 文件：483.53 Kbytes Page：5 Pages | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP 文件：483.53 Kbytes Page：5 Pages | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP 文件：483.53 Kbytes Page：5 Pages | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP 文件：483.53 Kbytes Page：5 Pages | Micrel 麦瑞半导体 | | ||
封装/外壳：20-SOIC（0.295"，7.50mm 宽） 包装：管件 描述：IC CLOCK GEN 3.3V/5V 20-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器 | Microchip 微芯科技 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP 文件：483.53 Kbytes Page：5 Pages | Micrel 麦瑞半导体 | | ||
封装/外壳：20-SOIC（0.295"，7.50mm 宽） 包装：管件 描述：IC CLOCK GEN 3.3V/5V 20-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器 | Microchip 微芯科技 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP 文件：483.53 Kbytes Page：5 Pages | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP 文件：483.53 Kbytes Page：5 Pages | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP 文件：483.53 Kbytes Page：5 Pages | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP 文件：483.53 Kbytes Page：5 Pages | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP 文件：483.53 Kbytes Page：5 Pages | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP 文件：483.53 Kbytes Page：5 Pages | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP 文件：483.53 Kbytes Page：5 Pages | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP 文件：483.53 Kbytes Page：5 Pages | Micrel 麦瑞半导体 | |
SY100S838产品属性
- 类型
描述
- 型号
SY100S838
- 功能描述
IC CLOCK GEN 3.3V/5V 20-SOIC
- RoHS
否
- 类别
集成电路(IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器
- 系列
Precision Edge®
- 标准包装
27
- 系列
Precision Edge®
- 类型
频率合成器
- PLL
是
- 输入
PECL，晶体
- 输出
PECL
- 电路数
1 比率 -
- 1
1 差分 -
- 输出
无/是 频率 -
- 最大
800MHz
- 除法器/乘法器
是/无
- 电源电压
3.135 V ~ 5.25 V
- 工作温度
0°C ~ 85°C
- 安装类型
表面贴装
- 封装/外壳
28-SOIC（0.295，7.50mm 宽）
- 供应商设备封装
28-SOIC
- 包装
管件
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
SYNERGY |
2024+ |
SMD |
50000 |
原装现货 |
|||
Microchip |
22+ |
20SOIC |
9000 |
原厂渠道,现货配单 |
|||
MICROCHIP/微芯 |
18+ |
SOIC20 |
6522 |
全新原装现货,可出样品,可开增值税发票 |
|||
MICREL/麦瑞 |
24+ |
SOIC-20 |
5000 |
全新原装正品现货 假一赔十 |
|||
24+ |
SMD20 |
6 |
本站现库存 |
||||
SYNERGY |
20+ |
SOP |
2960 |
诚信交易大量库存现货 |
|||
SYERGY |
24+ |
SOP |
9600 |
原装现货,优势供应,支持实单! |
|||
SYNERGY |
08+ |
SMD |
210 |
普通 |
|||
Microchip Technology |
24+ |
20-SOIC |
56200 |
一级代理/放心采购 |
|||
MICREL |
25+ |
SOIC-20 |
4 |
只做原装进口!正品支持实单! |
SY100S838规格书下载地址
SY100S838参数引脚图相关
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- SY15-S3
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- SY107M050AG3AAKPLP
- SY100S863JZ
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- SY100S834ZG
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- SY100S815ZH
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- SY100S391JZ
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- SY100S351JZ
- SY100S351JY
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- SY05-HF
- SY01-S3
- SXXNF1
- SXXNE1
- SXXND1
- SXXNC1
- SXXNB1
- SXXNA1
- SXXHR6
- SXXHR55
- SXXHR41
- SXXHR26
- SXXHR20
- SXXHR16
- SXXHR14
- SXXHN6
- SXXHN55
- SXXHN41
- SXXHN26
- SXXHN20
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DdatasheetPDF页码索引
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