位置：首页 > IC中文资料第1763页 > SY100S838
SY100S838价格
参考价格：￥22.7027
型号：SY100S838LZG 品牌：Micrel 备注：这里有SY100S838多少钱，2025年最近7天走势，今日出价，今日竞价，SY100S838批发/采购报价，SY100S838行情走势销售排行榜，SY100S838报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
SY100S838 | (첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 |   | |
SY100S838 | (첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP 文件：483.53 Kbytes Page：5 Pages | Micrel 麦瑞半导体 | | |
SY100S838 | (÷1, ÷2/3) OR (÷2, ÷4/6) CLOCK GENERATION CHIP | Microchip 微芯科技 | | |
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP 文件：483.53 Kbytes Page：5 Pages | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP 文件：483.53 Kbytes Page：5 Pages | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP 文件：483.53 Kbytes Page：5 Pages | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP 文件：483.53 Kbytes Page：5 Pages | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP 文件：483.53 Kbytes Page：5 Pages | Micrel 麦瑞半导体 | | ||
封装/外壳：20-SOIC（0.295"，7.50mm 宽） 包装：管件 描述：IC CLOCK GEN 3.3V/5V 20-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器 | Microchip 微芯科技 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP 文件：483.53 Kbytes Page：5 Pages | Micrel 麦瑞半导体 | | ||
封装/外壳：20-SOIC（0.295"，7.50mm 宽） 包装：管件 描述：IC CLOCK GEN 3.3V/5V 20-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器 | Microchip 微芯科技 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP 文件：483.53 Kbytes Page：5 Pages | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP 文件：483.53 Kbytes Page：5 Pages | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP 文件：483.53 Kbytes Page：5 Pages | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP 文件：483.53 Kbytes Page：5 Pages | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP 文件：483.53 Kbytes Page：5 Pages | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP 文件：483.53 Kbytes Page：5 Pages | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP 文件：483.53 Kbytes Page：5 Pages | Micrel 麦瑞半导体 | | ||
(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP 文件：483.53 Kbytes Page：5 Pages | Micrel 麦瑞半导体 | |
SY100S838产品属性
- 类型
描述
- 型号
SY100S838
- 功能描述
IC CLOCK GEN 3.3V/5V 20-SOIC
- RoHS
否
- 类别
集成电路(IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器
- 系列
Precision Edge®
- 标准包装
27
- 系列
Precision Edge®
- 类型
频率合成器
- PLL
是
- 输入
PECL，晶体
- 输出
PECL
- 电路数
1 比率 -
- 1
1 差分 -
- 输出
无/是 频率 -
- 最大
800MHz
- 除法器/乘法器
是/无
- 电源电压
3.135 V ~ 5.25 V
- 工作温度
0°C ~ 85°C
- 安装类型
表面贴装
- 封装/外壳
28-SOIC（0.295，7.50mm 宽）
- 供应商设备封装
28-SOIC
- 包装
管件
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
MICREL |
13+ |
SOIC-20 |
4 |
一级代理,专注军工、汽车、医疗、工业、新能源、电力 |
|||
MREL/麦瑞 |
24+ |
NA/ |
3333 |
原厂直销,现货供应,账期支持! |
|||
SYNERGY |
25+ |
SOP20 |
54658 |
百分百原装现货 实单必成 |
|||
MICREL |
2016+ |
SOP-20 |
8880 |
只做原装,假一罚十,公司可开17%增值税发票! |
|||
Micrel(麦瑞) |
23+ |
NA |
20094 |
正纳10年以上分销经验原装进口正品做服务做口碑有支持 |
|||
MICROCHIP/微芯 |
18+ |
SOIC20 |
6522 |
全新原装现货,可出样品,可开增值税发票 |
|||
Microchip |
22+ |
20SOIC |
9000 |
原厂渠道,现货配单 |
|||
MICREL |
23+ |
NA |
2330 |
专做原装正品,假一罚百! |
|||
MicrelInc |
25+23+ |
20-SOIC |
12848 |
绝对原装正品全新进口深圳现货 |
|||
SYNERGY |
2025+ |
SOP |
3827 |
全新原厂原装产品、公司现货销售 |
SY100S838芯片相关品牌
SY100S838规格书下载地址
SY100S838参数引脚图相关
- tda8023tt
- tda7294
- tda6101
- tda2822m
- tda2822
- tda2030功放电路图
- tda2030功放电路
- tda2030a
- tda2030
- tda2003功放电路图
- tda16846
- t7272
- t680
- t5007
- t5006
- t4242
- t40
- t2222
- t2010
- t100k
- SY3317
- SY320
- SY31X
- SY31W
- SY31P
- SY31J
- SY31GN
- SY31D
- SY31A
- SY306
- SY305
- SY302
- SY300
- SY-24-K
- SY2333
- SY2332
- SY171
- SY15-S3
- SY1316
- SY-12-K
- SY10E141JY
- SY10E137JZ
- SY10E131JY
- SY10E122JY
- SY10E116JY
- SY10E112JY
- SY10E111LJZ
- SY10E111LEJZ
- SY10E111JY
- SY10E111AJY
- SY10E111AEJY
- SY10E107JZ
- SY10E104JY
- SY10E101JY
- SY10E016JY
- SY107M050AG3AAKPLP
- SY100S863JZ
- SY100S839VZG
- SY100S838ZG
- SY100S838LZG
- SY100S834ZG
- SY100S834LZG
- SY100S815ZH
- SY100S811ZH
- SY100S391JZ
- SY100S363JZ
- SY100S351JZ
- SY100S351JY
- SY100S331JZ
- SY100S325JY
- SY100S324JY
- SY100S322JZ
- SY100S314JZ
- SY100S304JZ
- SY100HA643JY
- SY100H842ZH
- SY100H842LZG
- SY100H841LZH
- SY100H646LJZ
- SY100H641LJZ
- SY05-HF
- SY01-S3
- SXXNF1
- SXXNE1
- SXXND1
- SXXNC1
- SXXNB1
- SXXNA1
- SXXHR6
- SXXHR55
- SXXHR41
- SXXHR26
- SXXHR20
- SXXHR16
- SXXHR14
- SXXHN6
- SXXHN55
- SXXHN41
- SXXHN26
- SXXHN20
SY100S838数据表相关新闻
SY4S-51F1 夹，压紧 RY 系列插座
SY4S-51F1
2023-3-10SY2S-02F1 夹，压紧 RY 系列插座
SY2S-02F1
2023-3-10SY100EP195VTG-TR
优势渠道
2023-2-24SY22604KAC
SY22604KAC，全新.当天发货或门市自取，如需了解更多产品信息联系我们.零七五五.八二七三二二九一企鹅:一一七四零五二三五三，V:八七六八零五五八.
2021-9-29SY100ELT23ZGTR 原装现货
SY100ELT23ZGTR 可做含税，支持实单
2021-9-17SY100S363JZTR 编码器、解码器、复用器和解复用器
SY100S363JZTR 编码器、解码器、复用器和解复用器
2020-10-22
DdatasheetPDF页码索引
- P1
- P2
- P3
- P4
- P5
- P6
- P7
- P8
- P9
- P10
- P11
- P12
- P13
- P14
- P15
- P16
- P17
- P18
- P19
- P20
- P21
- P22
- P23
- P24
- P25
- P26
- P27
- P28
- P29
- P30
- P31
- P32
- P33
- P34
- P35
- P36
- P37
- P38
- P39
- P40
- P41
- P42
- P43
- P44
- P45
- P46
- P47
- P48
- P49
- P50
- P51
- P52
- P53
- P54
- P55
- P56
- P57
- P58
- P59
- P60
- P61
- P62
- P63
- P64
- P65
- P66
- P67
- P68
- P69
- P70
- P71
- P72
- P73
- P74
- P75
- P76
- P77
- P78
- P79
- P80
- P81
- P82
- P83
- P84
- P85
- P86
- P87
- P88
- P89
- P90
- P91
- P92
- P93
- P94
- P95
- P96
- P97
- P98
- P99
- P100
- P101
- P102
- P103
- P104
- P105
- P106
- P107
