(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP

文件：483.53 Kbytes Page：5 Pages

(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP

DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by

(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP

文件：483.53 Kbytes Page：5 Pages

(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP

DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by

(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP

DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by

(첨1, 첨2/3) OR (첨2, 첨4/6) CLOCK GENERATION CHIP

文件：483.53 Kbytes Page：5 Pages