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| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
SSTUM32868ET | 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications | ETC 知名厂家 | ETC |   |
封装/外壳：176-TFBGA 包装：托盘 描述：IC REG BUFFER CONFIG 176TFBGA 集成电路（IC） 专用逻辑器件 | ETC 知名厂家 | ETC | | |
1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications | ETC 知名厂家 | ETC | | |
1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications | ETC 知名厂家 | ETC | | |
封装/外壳：176-TFBGA 包装：托盘 描述：IC BUFFER 1.8V 25BIT 176-TFBGA 集成电路（IC） 专用逻辑器件 | ETC 知名厂家 | ETC | | |
1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications | ETC 知名厂家 | ETC | | |
1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications | ETC 知名厂家 | ETC | | |
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 CONFIDENTIAL Features • 28-bit 1:2 registered buffer with parity check functionality • Supports SSTL_18 JEDEC specification on data inputs and outputs • Supports LVCMOS switching levels on CSGEN and RESET inputs • Low voltage operation: VDD = 1.7V to 1.9V • Available in 176-ball LFBGA package | RENESAS 瑞萨 | | ||
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description This 28-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation. All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All outputs are edge-controlle | IDT | | ||
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description This 28-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation. All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All outputs are edge-controlle | IDT | | ||
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 CONFIDENTIAL Features • 28-bit 1:2 registered buffer with parity check functionality • Supports SSTL_18 JEDEC specification on data inputs and outputs • Supports LVCMOS switching levels on CSGEN and RESET inputs • Low voltage operation: VDD = 1.7V to 1.9V • Available in 176-ball LFBGA package | RENESAS 瑞萨 | | ||
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description This 28-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation. All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All outputs are edge-controlle | IDT | |
SSTUM32868ET产品属性
- 类型
描述
- 型号
SSTUM32868ET
- 功能描述
寄存器 REG BUF/PARITY FOR DDR2-800+
- RoHS
否
- 制造商
NXP Semiconductors
- 逻辑类型
CMOS
- 逻辑系列
HC
- 电路数量
1
- 最大时钟频率
36 MHz
- 高电平输出电流
- 7.8 mA
- 低电平输出电流
7.8 mA
- 电源电压-最大
6 V
- 最大工作温度
+ 125 C
- 封装/箱体
SOT-38
- 封装
Tube
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
恩XP |
22+ |
176TFBGA (6x15) |
9000 |
原厂渠道,现货配单 |
|||
Rochester |
25+ |
电联咨询 |
7800 |
公司现货,提供拆样技术支持 |
|||
恩XP |
24+ |
BGA |
990000 |
明嘉莱只做原装正品现货 |
|||
恩XP |
24+ |
BGA |
25836 |
新到现货，只做全新原装正品 |
|||
SI |
25+ |
SOP8 |
2000 |
百分百原装正品 真实公司现货库存 本公司只做原装 可 |
|||
24+ |
N/A |
76000 |
一级代理-主营优势-实惠价格-不悔选择 |
||||
恩XP |
24+ |
176-TFBGA(6x15) |
56200 |
一级代理/放心采购 |
|||
恩XP |
25+ |
SOT932 |
188600 |
全新原厂原装正品现货 欢迎咨询 |
|||
恩XP |
23+ |
BGA |
21200 |
全新原装正品现货,支持订货 |
|||
恩XP |
21+ |
BGA |
10000 |
原装现货假一罚十 |
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2012-11-8
DdatasheetPDF页码索引
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