DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

FEATURES · Controlled Baseline – One Assembly/Test Site, One Fabrication Site · Extended Temperature Performance of– 55°C to 125°C · Enhanced Diminishing Manufacturing Sources (DMS) Support · Enhanced Product-Change Notification · Qualification Pedigree (1) · 2-V to 5.5-V VCC Operation

封装/外壳：14-TSSOP（0.173"，4.40mm 宽） 功能：设置（预设）和复位 包装：管件 描述：IC FF D-TYPE DUAL 1BIT 14TSSOP 集成电路（IC） 触发器

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

文件：506.49 Kbytes Page：14 Pages

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

FEATURES · Controlled Baseline – One Assembly/Test Site, One Fabrication Site · Extended Temperature Performance of– 55°C to 125°C · Enhanced Diminishing Manufacturing Sources (DMS) Support · Enhanced Product-Change Notification · Qualification Pedigree (1) · 2-V to 5.5-V VCC Operation

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74LV74 is a dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock trans

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. FEATURES • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Ty

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. FEATURES • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Ty

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74LV74 is a dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock trans

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

文件：444.43 Kbytes Page：16 Pages