74LV74D价格
参考价格：￥0.6612
型号：74LV74D,112 品牌：Philips Semiconducto 备注：这里有74LV74D多少钱，2026年最近7天走势，今日出价，今日竞价，74LV74D批发/采购报价，74LV74D行情走势销售排行榜，74LV74D报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
74LV74D | Dual D-type flip-flop with set and reset; positive-edge trigger DESCRIPTION The 74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. FEATURES • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Ty | PHILIPS 飞利浦 |   | |
74LV74D | Dual D-type flip-flop with set and reset; positive-edge trigger 1. General description The 74LV74 is a dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock trans | NEXPERIA 安世 | | |
74LV74D | Dual D-type flip-flop with set and reset; positive-edge trigger The 74LV74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.\n The set and reset are asynchronous active LOW inputs that operate independently of the clock input. Informatio • Wide operating voltage: 1.0 V to 5.5 V\n• Optimized for Low Voltage applications: 1.0 V to 3.6 V\n• Direct interface with TTL levels (2.7 V to 3.6 V)\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n• Specified from -40°C to +85°C and from -40°C to +125°C; | NEXPERIA 安世 | | |
D-Type Flip-Flops Dual D-type flip-flop with set and reset; positive-edge trigger - The 74LV74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inp ·Wide operating voltage: 1.0 V to 5.5 V\n·Optimized for Low Voltage applications: 1.0 V to 3.6 V\n·Direct interface with TTL levels (2.7 V to 3.6 V)\n·ESD protection:·HBM JESD22-A114F exceeds 2000 V\n·MM JESD22-A115-A exceeds 200 V; | NEXPERIA 安世 | | ||
Dual D-type flip-flop with set and reset; positive-edge trigger DESCRIPTION The 74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. FEATURES • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Ty | PHILIPS 飞利浦 | | ||
Dual D-type flip-flop with set and reset; positive-edge trigger The 74LV74-Q100 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.\n The set and reset are asynchronous active LOW inputs that operate independently of the clock input. Infor • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Wide supply voltage range from 1.0 V to 5.5 V\n• Optimized for low voltage applications: 1.0 V to 3.6 V\n• Direct interface with TTL levels (2.7 V to 3.6 V)\n• ES; | NEXPERIA 安世 | | ||
封装/外壳：14-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE DUAL 1BIT 14SO 集成电路（IC） 触发器 | ETC 知名厂家 | ETC | | |
封装/外壳：14-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：管件 描述：IC FF D-TYPE DUAL 1BIT 14SO 集成电路（IC） 触发器 | ETC 知名厂家 | ETC | | |
Dual D-type flip-flop with set and reset; positive-edge trigger 文件：1.05556 Mbytes Page：17 Pages | NEXPERIA 安世 | | ||
Dual D-type flip-flop with set and reset; positive-edge trigger DESCRIPTION The 74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. FEATURES • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Ty | PHILIPS 飞利浦 | | ||
Dual D-type flip-flop with set and reset; positive-edge trigger DESCRIPTION The 74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. FEATURES • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Ty | PHILIPS 飞利浦 | | ||
Dual D-type flip-flop with set and reset; positive-edge trigger DESCRIPTION The 74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. FEATURES • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Ty | PHILIPS 飞利浦 | |
74LV74D产品属性
- 类型
描述
- VCC (V)：
1.0 - 5.5
- Logic switching levels：
TTL
- Output drive capability (mA)：
± 12
- tpd (ns)：
11
- fmax (MHz)：
75
- Power dissipation considerations：
low
- Tamb (°C)：
-40~125
- Rth(j-a) (K/W)：
83
- Ψth(j-top) (K/W)：
3.7
- Rth(j-c) (K/W)：
41
- Package name：
SO14
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
PHI |
SOP |
2500 |
正品原装--自家现货-实单可谈 |
||||
Nexperia USA Inc. |
23+ |
14-SO |
5000 |
原装正品 正规报关 可开增值税票 |
|||
PHI |
02+ |
SOP |
339 |
原装现货海量库存欢迎咨询 |
|||
ph |
24+ |
N/A |
6980 |
原装现货,可开13%税票 |
|||
NEXPERIA/安世 |
23+ |
SOT108 |
6000 |
原装正品假一罚百!可开增票! |
|||
TI |
24+ |
NA |
7500 |
只做原装正品现货 欢迎来电查询15919825718 |
|||
PHI |
2402+ |
SOP |
8324 |
原装正品!实单价优! |
|||
恩XP |
25+ |
30000 |
房间原装现货特价热卖,有单详谈 |
||||
PHI |
0516+ |
SSOP |
4020 |
全新 发货1-2天 |
|||
PHI |
25+ |
3.9mm |
2987 |
只售原装自家现货!诚信经营!欢迎来电! |
74LV74D规格书下载地址
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74LS90：十进制计数器;十二分频计数器;4位二进制计数器 SN54/74LS90，SN54/74LS92和SN54/74LS93高速4位波纹型计数器，分割成两部分。每个计数器都有一个鸿沟由两节和一个分五（LS90），除以六（LS92）或 除以个（LS93）部分是由高向低过渡触发时钟输入。每一节都可以单独使用，或绑在了一起（问到CP），形成BCD，双向五元，模12模16计数器。所有 计数器有一个2输入门控主复位（清除），和LS90还有一个2输入与门控主设定（预设9）。 特点： •低功耗。通常为45兆瓦
2012-11-9
DdatasheetPDF页码索引
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