74LV74D价格
参考价格：￥0.6612
型号：74LV74D,112 品牌：Philips Semiconducto 备注：这里有74LV74D多少钱，2026年最近7天走势，今日出价，今日竞价，74LV74D批发/采购报价，74LV74D行情走势销售排行榜，74LV74D报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
74LV74D | Dual D-type flip-flop with set and reset; positive-edge trigger DESCRIPTION The 74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. FEATURES • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Ty | PHILIPS 飞利浦 |   | |
74LV74D | Dual D-type flip-flop with set and reset; positive-edge trigger 1. General description The 74LV74 is a dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock trans | NEXPERIA 安世 | | |
74LV74D | Dual D-type flip-flop with set and reset; positive-edge trigger The 74LV74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.\n The set and reset are asynchronous active LOW inputs that operate independently of the clock input. Informatio • Wide operating voltage: 1.0 V to 5.5 V\n• Optimized for Low Voltage applications: 1.0 V to 3.6 V\n• Direct interface with TTL levels (2.7 V to 3.6 V)\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n• Specified from -40°C to +85°C and from -40°C to +125°C; | NEXPERIA 安世 | | |
D-Type Flip-Flops Dual D-type flip-flop with set and reset; positive-edge trigger - The 74LV74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inp ·Wide operating voltage: 1.0 V to 5.5 V\n·Optimized for Low Voltage applications: 1.0 V to 3.6 V\n·Direct interface with TTL levels (2.7 V to 3.6 V)\n·ESD protection:·HBM JESD22-A114F exceeds 2000 V\n·MM JESD22-A115-A exceeds 200 V; | NEXPERIA 安世 | | ||
Dual D-type flip-flop with set and reset; positive-edge trigger DESCRIPTION The 74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. FEATURES • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Ty | PHILIPS 飞利浦 | | ||
Dual D-type flip-flop with set and reset; positive-edge trigger The 74LV74-Q100 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.\n The set and reset are asynchronous active LOW inputs that operate independently of the clock input. Infor • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Wide supply voltage range from 1.0 V to 5.5 V\n• Optimized for low voltage applications: 1.0 V to 3.6 V\n• Direct interface with TTL levels (2.7 V to 3.6 V)\n• ES; | NEXPERIA 安世 | | ||
封装/外壳：14-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE DUAL 1BIT 14SO 集成电路（IC） 触发器 | ETC 知名厂家 | ETC | | |
封装/外壳：14-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：管件 描述：IC FF D-TYPE DUAL 1BIT 14SO 集成电路（IC） 触发器 | ETC 知名厂家 | ETC | | |
Dual D-type flip-flop with set and reset; positive-edge trigger 文件：1.05556 Mbytes Page：17 Pages | NEXPERIA 安世 | | ||
Dual D-type flip-flop with set and reset; positive-edge trigger DESCRIPTION The 74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. FEATURES • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Ty | PHILIPS 飞利浦 | | ||
Dual D-type flip-flop with set and reset; positive-edge trigger DESCRIPTION The 74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. FEATURES • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Ty | PHILIPS 飞利浦 | | ||
Dual D-type flip-flop with set and reset; positive-edge trigger DESCRIPTION The 74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. FEATURES • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Ty | PHILIPS 飞利浦 | |
74LV74D产品属性
- 类型
描述
- VCC (V)：
1.0 - 5.5
- Logic switching levels：
TTL
- Output drive capability (mA)：
± 12
- tpd (ns)：
11
- fmax (MHz)：
75
- Power dissipation considerations：
low
- Tamb (°C)：
-40~125
- Rth(j-a) (K/W)：
83
- Ψth(j-top) (K/W)：
3.7
- Rth(j-c) (K/W)：
41
- Package name：
SO14
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
恩XP |
26+ |
30000 |
房间原装现货特价热卖,有单详谈 |
||||
恩XP |
2016+ |
SOP-14 |
3500 |
只做原装,假一罚十,公司可开17%增值税发票! |
|||
恩XP |
24+ |
SOP14 |
80000 |
只做自己库存 全新原装进口正品假一赔百 可开13%增 |
|||
PHI |
22+ |
SOP |
8000 |
原装正品支持实单 |
|||
恩XP |
21+ |
SOT-753 |
8080 |
只做原装,质量保证 |
|||
PHI |
25+ |
SOP14 |
3200 |
全新原装、诚信经营、公司现货销售 |
|||
Nexperia USA Inc. |
24+25+ |
16500 |
全新原厂原装现货!受权代理!可送样可提供技术支持! |
||||
PHI |
2402+ |
SOP |
8324 |
原装正品!实单价优! |
|||
24+ |
5000 |
公司存货 |
|||||
PHI |
26+ |
SOP |
6895 |
原厂全新正品旗舰店优势现货 |
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DdatasheetPDF页码索引
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