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位置：首页 > IC中文资料 > 74LV74

74LV74价格

参考价格：￥0.6612

型号：74LV74D,112 品牌：Philips Semiconducto 备注：这里有74LV74多少钱，2026年最近7天走势，今日出价，今日竞价，74LV74批发/采购报价，74LV74行情走势销售排行榜，74LV74报价。
型号 功能描述 生产厂家 企业 LOGO 操作
74LV74

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. FEATURES • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Ty

PHILIPS

飞利浦

74LV74

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74LV74 is a dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock trans

NEXPERIA

安世

74LV74D

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74LV74 is a dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock trans

NEXPERIA

安世

74LV74D

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. FEATURES • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Ty

PHILIPS

飞利浦

74LV74DB

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. FEATURES • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Ty

PHILIPS

飞利浦

74LV74DB

D-Type Flip-Flops

Dual D-type flip-flop with set and reset; positive-edge trigger - The 74LV74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inp ·Wide operating voltage: 1.0 V to 5.5 V\n·Optimized for Low Voltage applications: 1.0 V to 3.6 V\n·Direct interface with TTL levels (2.7 V to 3.6 V)\n·ESD protection:·HBM JESD22-A114F exceeds 2000 V\n·MM JESD22-A115-A exceeds 200 V;

NEXPERIA

安世

74LV74D-Q100

Dual D-type flip-flop with set and reset; positive-edge trigger

The 74LV74-Q100 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.\n The set and reset are asynchronous active LOW inputs that operate independently of the clock input. Infor • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Wide supply voltage range from 1.0 V to 5.5 V\n• Optimized for low voltage applications: 1.0 V to 3.6 V\n• Direct interface with TTL levels (2.7 V to 3.6 V)\n• ES;

NEXPERIA

安世

74LV74N

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. FEATURES • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Ty

PHILIPS

飞利浦

74LV74PW

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. FEATURES • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Ty

PHILIPS

飞利浦

74LV74PW

Dual D-type flip-flop with set and reset; positive-edge trigger

The 74LV74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.\n The set and reset are asynchronous active LOW inputs that operate independently of the clock input. Informatio • Wide operating voltage: 1.0 V to 5.5 V\n• Optimized for Low Voltage applications: 1.0 V to 3.6 V\n• Direct interface with TTL levels (2.7 V to 3.6 V)\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n• Specified from -40°C to +85°C and from -40°C to +125°C;

NEXPERIA

安世

74LV74PW

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74LV74 is a dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock trans

NEXPERIA

安世

74LV74PWDH

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. FEATURES • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Ty

PHILIPS

飞利浦

74LV74A

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

文件：444.43 Kbytes Page：16 Pages

TI

德州仪器

74LV74D,118

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE DUAL 1BIT 14SO 集成电路（IC） 触发器

ETC

知名厂家

74LV74D/AUJ

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：管件 描述：IC FF D-TYPE DUAL 1BIT 14SO 集成电路（IC） 触发器

ETC

知名厂家

74LV74D-Q100

Dual D-type flip-flop with set and reset; positive-edge trigger

文件：1.05556 Mbytes Page：17 Pages

NEXPERIA

安世

74LV74PW-Q100

Dual D-type flip-flop with set and reset; positive-edge trigger

文件：1.05556 Mbytes Page：17 Pages

NEXPERIA

安世

74LV74-Q100

Dual D-type flip-flop with set and reset; positive-edge trigger

文件：1.05556 Mbytes Page：17 Pages

NEXPERIA

安世

74LV74产品属性

  • 类型

    描述

  • VCC (V)：

    1.0 - 5.5

  • Logic switching levels：

    TTL

  • Output drive capability (mA)：

    ± 12

  • tpd (ns)：

    11

  • fmax (MHz)：

    75

  • Power dissipation considerations：

    low

  • Tamb (°C)：

    -40~125

  • Rth(j-a) (K/W)：

    83

  • Ψth(j-top) (K/W)：

    3.7

  • Rth(j-c) (K/W)：

    41

  • Package name：

    SO14

74LV74供应商更多...

更新时间：2026-5-20 17:58:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
深圳市腾亿芯科技有限公司
74LV74PW.118
恩XP
25+
SMD
20000
原装
询价
深圳市科恒伟业电子有限公司
74LV74PW
恩XP
2450+
TSSOP
6540
只做原装正品假一赔十为客户做到零风险!!
询价
深圳市得捷芯城科技有限公司
74LV74PW-Q100J
Nexperia(安世)
25+
TSSOP-14
21000
原装正品现货,原厂订货,可支持含税原型号开票。
询价
深圳市拓亿芯电子有限公司
74LV74D
PHI
25+
SOP14
18000
全新原装现货,假一赔十
询价
深圳市赛美科科技有限公司
74LV74PW-T
PHI
TSSOP
68500
一级代理 原装正品假一罚十价格优势长期供货
询价
深圳市卓越微芯电子有限公司
74LV74PW(ROHS)
PHI
25+
TSSOP
1596
百分百原装正品 真实公司现货库存 本公司只做原装 可
询价
深圳市华斯顿科技有限公司
74LV74APWR
TI
25+23+
TSSOP
54410
绝对原装正品现货,全新深圳原装进口现货
询价
深圳市昌和盛利电子有限公司
74LV74PW
ON
26+
TSSOP
12335
代理全系列销售,全新原装正品,价格优势,长期供应,量大可订
询价
深圳市胜彬电子有限公司
74LV74PW
PHI
22+
TSSOP
8000
原装正品支持实单
询价
深圳市美思瑞电子科技有限公司
74LV74D,118
NEXPERIA/安世
22+
N/A
7500
现货,原厂原装假一罚十!
询价

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74LV74规格书下载地址

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DdatasheetPDF页码索引

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