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SN74LS37价格
参考价格：￥2.4740
型号：SN74LS373DW 品牌：Texas 备注：这里有SN74LS37多少钱，2025年最近7天走势，今日出价，今日竞价，SN74LS37批发/采购报价，SN74LS37行情走势销售排行榜，SN74LS37报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
SN74LS37 | QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS 文件：249.42 Kbytes Page：7 Pages | TI 德州仪器 |   | |
SN74LS37 | 4 通道、2 输入、4.75V 至 5.25V 双极与非门 | TI 德州仪器 | | |
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI 德州仪器 | | ||
Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is | ONSEMI 安森美半导体 | | ||
Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is | ONSEMI 安森美半导体 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI 德州仪器 | | ||
OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT The SN54 /74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (datachanges asynchronously) when Latch Enable (LE) | Motorola 摩托罗拉 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI 德州仪器 | | ||
Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is | ONSEMI 安森美半导体 | | ||
Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is | ONSEMI 安森美半导体 | | ||
Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is | ONSEMI 安森美半导体 | | ||
Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is | ONSEMI 安森美半导体 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI 德州仪器 | | ||
OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT The SN54 /74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (datachanges asynchronously) when Latch Enable (LE) | Motorola 摩托罗拉 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI 德州仪器 | | ||
Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is | ONSEMI 安森美半导体 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI 德州仪器 | | ||
OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT The SN54 /74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (datachanges asynchronously) when Latch Enable (LE) | Motorola 摩托罗拉 | | ||
Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is | ONSEMI 安森美半导体 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI 德州仪器 | | ||
Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is | ONSEMI 安森美半导体 | | ||
Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is | ONSEMI 安森美半导体 | | ||
Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is | ONSEMI 安森美半导体 | | ||
Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is | ONSEMI 安森美半导体 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI 德州仪器 | | ||
OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT The SN54 /74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (datachanges asynchronously) when Latch Enable (LE) | Motorola 摩托罗拉 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and | TI 德州仪器 | | ||
4.BIT BISTABLE LATCHES Supply Voltage and Ground on Corner Pins To Simplify P-C Board Layout description The SN54LS376 and SN74LS376 bistable latches are electrically and functionally identical to the SN54LS75 and SN74LS75, respectively. Only the arrangement of the terminals hes been changed in the SN54L5375 an | TI 德州仪器 | | ||
4.BIT BISTABLE LATCHES Supply Voltage and Ground on Corner Pins To Simplify P-C Board Layout description The SN54LS376 and SN74LS376 bistable latches are electrically and functionally identical to the SN54LS75 and SN74LS75, respectively. Only the arrangement of the terminals hes been changed in the SN54L5375 an | TI 德州仪器 | | ||
4-BIT D LATCH The SN54/74LS375 is a 4-Bit D-Type Latch for use as temporary storage for binary information between processing limits and input/output or indicator units. When the Enable (E) is HIGH, information present at the D input will be transferred to the Q output and, if E is HIGH, the Q output will follo | Motorola 摩托罗拉 | | ||
4.BIT BISTABLE LATCHES Supply Voltage and Ground on Corner Pins To Simplify P-C Board Layout description The SN54LS376 and SN74LS376 bistable latches are electrically and functionally identical to the SN54LS75 and SN74LS75, respectively. Only the arrangement of the terminals hes been changed in the SN54L5375 an | TI 德州仪器 | | ||
4.BIT BISTABLE LATCHES Supply Voltage and Ground on Corner Pins To Simplify P-C Board Layout description The SN54LS376 and SN74LS376 bistable latches are electrically and functionally identical to the SN54LS75 and SN74LS75, respectively. Only the arrangement of the terminals hes been changed in the SN54L5375 an | TI 德州仪器 | | ||
4-BIT D LATCH The SN54/74LS375 is a 4-Bit D-Type Latch for use as temporary storage for binary information between processing limits and input/output or indicator units. When the Enable (E) is HIGH, information present at the D input will be transferred to the Q output and, if E is HIGH, the Q output will follo | Motorola 摩托罗拉 | | ||
4.BIT BISTABLE LATCHES Supply Voltage and Ground on Corner Pins To Simplify P-C Board Layout description The SN54LS376 and SN74LS376 bistable latches are electrically and functionally identical to the SN54LS75 and SN74LS75, respectively. Only the arrangement of the terminals hes been changed in the SN54L5375 an | TI 德州仪器 | | ||
LOW POWER SCHOTTKY The SN74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. • 8-Bit High Speed Parallel Registers • Positive Edge-Triggered D-Type Flip Flops • F | ONSEMI 安森美半导体 | | ||
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54/74LS378 is a 6-Bit Register with a buffered common enable. This device is similar | Motorola 摩托罗拉 | | ||
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54/74LS378 is a 6-Bit Register with a buffered common enable. This device is similar | Motorola 摩托罗拉 | | ||
LOW POWER SCHOTTKY The SN74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. • 8-Bit High Speed Parallel Registers • Positive Edge-Triggered D-Type Flip Flops • F | ONSEMI 安森美半导体 | | ||
LOW POWER SCHOTTKY The SN74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. • 8-Bit High Speed Parallel Registers • Positive Edge-Triggered D-Type Flip Flops • F | ONSEMI 安森美半导体 | | ||
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54/74LS378 is a 6-Bit Register with a buffered common enable. This device is similar | Motorola 摩托罗拉 | | ||
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54/74LS378 is a 6-Bit Register with a buffered common enable. This device is similar | Motorola 摩托罗拉 | | ||
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54/74LS378 is a 6-Bit Register with a buffered common enable. This device is similar | Motorola 摩托罗拉 | | ||
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54/74LS378 is a 6-Bit Register with a buffered common enable. This device is similar | Motorola 摩托罗拉 | | ||
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54/74LS378 is a 6-Bit Register with a buffered common enable. This device is similar | Motorola 摩托罗拉 | | ||
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54/74LS378 is a 6-Bit Register with a buffered common enable. This device is similar | Motorola 摩托罗拉 | | ||
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54/74LS378 is a 6-Bit Register with a buffered common enable. This device is similar | Motorola 摩托罗拉 | | ||
QUAD 2-INPUT NAND BUFFER
| Motorola 摩托罗拉 | | ||
QUAD 2-INPUT NAND BUFFER
| Motorola 摩托罗拉 | | ||
具有三态输出的八路 D 类透明锁存器 | TI 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件：1.43118 Mbytes Page：30 Pages | TI 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件：331.48 Kbytes Page：24 Pages | TI 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件：242.39 Kbytes Page：10 Pages | TI 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件：694.69 Kbytes Page：28 Pages | TI 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件：694.69 Kbytes Page：28 Pages | TI 德州仪器 | | ||
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 文件：331.48 Kbytes Page：24 Pages | TI 德州仪器 | |
| 替换型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
TRI-STATEE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops | NSCNational Semiconductor (TI) 美国国家半导体美国国家半导体公司 | NSC | | |
QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS | TI 德州仪器 | TI | | |
Quadruple 2-input Positive NAND Buffers | HitachiHitachi Semiconductor 日立日立公司 | Hitachi | | |
3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops | FairchildFairchild Semiconductor 仙童半导体飞兆/仙童半导体公司 | Fairchild | | |
Quadruple 2-input Positive NAND Buffers | RENESAS 瑞萨 | RENESAS | | |
Ouadruple 2-input Positive NAND Gates | HitachiHitachi Semiconductor 日立日立公司 | Hitachi | | |
Quadruple 2-input Positive NAND Buffers | HitachiHitachi Semiconductor 日立日立公司 | Hitachi | | |
Quadruple 2-input Positive NAND Buffers | RENESAS 瑞萨 | RENESAS | |
SN74LS37产品属性
- 类型
描述
- 型号
SN74LS37
- 功能描述
闭锁 Octal D-Type
- RoHS
否
- 制造商
Micrel
- 电路数量
1
- 逻辑类型
CMOS
- 逻辑系列
TTL
- 极性
Non-Inverting
- 输出线路数量
9
- 电源电压-最大
12 V
- 电源电压-最小
5 V
- 最大工作温度
+ 85 C
- 最小工作温度
- 40 C
- 封装/箱体
SOIC-16
- 封装
Reel
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
TI(德州仪器) |
24+ |
SOP16 |
935 |
只做原装,提供一站式配单服务,代工代料。BOM配单 |
|||
FAIRCHILD/仙童 |
25+ |
DIP20 |
154765 |
明嘉莱只做原装正品现货 |
|||
TI |
23+ |
SOP5.2 |
12560 |
受权代理!全新原装现货特价热卖! |
|||
TI |
98+ |
SOP20 |
2110 |
全新原装进口自己库存优势 |
|||
TEXASINSTRU |
24+ |
原厂封装 |
6843 |
原装现货假一罚十 |
|||
TI |
23+ |
SOP20 |
20000 |
全新原装假一赔十 |
|||
TI |
24+/25+ |
68 |
原装正品现货库存价优 |
||||
TI |
24+ |
DIP |
5000 |
TI一级代理商原装进口现货 |
|||
TI/德州仪器 |
25+ |
DIP |
12360 |
TI/德州仪器原装特价SN74LS37N即刻询购立享优惠#长期有货 |
|||
TI |
2121+ |
SOP-20 |
1000 |
全新原装公司现货
|
SN74LS37规格书下载地址
SN74LS37参数引脚图相关
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- SN74LS374NS
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- SN74LS374N
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- SN74LS374JD
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- SN74LS373N
- SN74LS373JS
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- SN74LS373JD
- SN74LS373J
- SN74LS373
- SN74LS368N
- SN74LS368J
- SN74LS368ANS
- SN74LS368ANDS
- SN74LS368AND
- SN74LS368AN
- SN74LS368AJS
- SN74LS368AJDS
- SN74LS368AJD
- SN74LS368AJ
- SN74LS368A
- SN74LS367N
- SN74LS367J
- SN74LS367AN-X
- SN74LS367ANS
- SN74LS367ANDS
- SN74LS367AND
- SN74LS367AN
- SN74LS367AJS
- SN74LS367AJDS
- SN74LS
- SN74L71
- SN74L44
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- SN74F86
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- SN74F51
- SN74F38
- SN74F37
- SN74F36
- SN74F32
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