HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS

文件：327.66 Kbytes Page：11 Pages

HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS

文件：52.06 Kbytes Page：4 Pages

HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS

文件：513.52 Kbytes Page：13 Pages

丝印代码：SN74LS173AN；4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

3-State Outputs Interface Directly With System Bus Gated Output-Control LInes for Enabling or Disabling the Outputs Fully Independent Clock Virtually Eliminates Restrictions for Operating in One of Two Modes: – Parallel Load – Do Nothing (Hold) For Application as Bus Buffer Registers Pac

丝印代码：SN74LS173AN；4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

3-State Outputs Interface Directly With System Bus Gated Output-Control LInes for Enabling or Disabling the Outputs Fully Independent Clock Virtually Eliminates Restrictions for Operating in One of Two Modes: – Parallel Load – Do Nothing (Hold) For Application as Bus Buffer Registers Pac

丝印代码：SN74LS174N；HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

丝印代码：SN74LS174N；HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

丝印代码：SN74LS175N；HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

丝印代码：SN74LS175N；HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

丝印代码：SN74LS175N；HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

4 x 4 REGISTER FILE OPEN-COLLECTOR

4 x 4 REGISTER FILE OPEN-COLLECTOR The TTL /MSI SN54 /74LS170 is a high-speed, low-power 4 x 4 Register File organized as four words by four bits. Separate read and write inputs, both address and enable, allow simultaneous read and write operation. Open-collector outputs make it possible to conn

4 x 4 REGISTER FILE OPEN-COLLECTOR

4 x 4 REGISTER FILE OPEN-COLLECTOR The TTL /MSI SN54 /74LS170 is a high-speed, low-power 4 x 4 Register File organized as four words by four bits. Separate read and write inputs, both address and enable, allow simultaneous read and write operation. Open-collector outputs make it possible to conn

4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

3-State Outputs Interface Directly With System Bus Gated Output-Control LInes for Enabling or Disabling the Outputs Fully Independent Clock Virtually Eliminates Restrictions for Operating in One of Two Modes: – Parallel Load – Do Nothing (Hold) For Application as Bus Buffer Registers Pac

丝印代码：LS173A；4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

3-State Outputs Interface Directly With System Bus Gated Output-Control LInes for Enabling or Disabling the Outputs Fully Independent Clock Virtually Eliminates Restrictions for Operating in One of Two Modes: – Parallel Load – Do Nothing (Hold) For Application as Bus Buffer Registers Pac

丝印代码：LS173A；4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

3-State Outputs Interface Directly With System Bus Gated Output-Control LInes for Enabling or Disabling the Outputs Fully Independent Clock Virtually Eliminates Restrictions for Operating in One of Two Modes: – Parallel Load – Do Nothing (Hold) For Application as Bus Buffer Registers Pac

4-BIT D-TYPE REGISTER WITH 3-STATE OUTPUTS

4-BIT D-TYPE REGISTERWITH 3-STATE OUTPUTS The SN54/74LS173A is a high-speed 4-BitRegister featuring 3-state outputs foruse in bus-organized systems. The clock is fully edge-triggered allowingeither a load from the D inputs ora hold (retain register contents) dependingon the state of the Input E

4-BIT D-TYPE REGISTER WITH 3-STATE OUTPUTS

4-BIT D-TYPE REGISTERWITH 3-STATE OUTPUTS The SN54/74LS173A is a high-speed 4-BitRegister featuring 3-state outputs foruse in bus-organized systems. The clock is fully edge-triggered allowingeither a load from the D inputs ora hold (retain register contents) dependingon the state of the Input E

具有清零端的六路 D 型触发器

These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the '175, 'LS175, and 'S175 feature complementary outputs from each flip-flop. Information at the D inputs meeting the setup time requirements is transfe • '174, 'LS174, 'S174 Contain Six Flip-Flops with Single-Rail Outputs\n• '175, 'LS175, 'S175 Contain Four Flip-Flops with Double-Rail Outputs\n• Three Performance Ranges Offered: See Table Lower Right\n• Buffered Clock and Direct Clear Inputs\n• Individual Data Input to Each Flip-Flop\n• Application;

HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

LOW POWER SCHOTTKY

The LSTTL/MSI SN74LS174 is a high speed Hex D Flip-Flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW to HIGH clock transition. The device has a Master Reset to simultaneously clear all flip-flops.

LOW POWER SCHOTTKY

The LSTTL/MSI SN74LS174 is a high speed Hex D Flip-Flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW to HIGH clock transition. The device has a Master Reset to simultaneously clear all flip-flops.

丝印代码：LS174；HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

HEX D FLIP-FLOP

The LSTTL/MSI SN54/74LS174 is a high speed Hex D Flip-Flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW to HIGH clock transition. The device has a Master Reset to simultaneously clear all flip-flo

丝印代码：LS174；HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

丝印代码：LS174；HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

HEX D FLIP-FLOP

The LSTTL/MSI SN54/74LS174 is a high speed Hex D Flip-Flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW to HIGH clock transition. The device has a Master Reset to simultaneously clear all flip-flo

LOW POWER SCHOTTKY

The LSTTL/MSI SN74LS174 is a high speed Hex D Flip-Flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW to HIGH clock transition. The device has a Master Reset to simultaneously clear all flip-flops.

丝印代码：74LS174；HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

丝印代码：74LS174；HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

LOW POWER SCHOTTKY

The LSTTL/MSI SN74LS175 is a high speed Quad D Flip-Flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW to HIGH clock transition. Both true and complemented outputs of each flip-flop are pro

LOW POWER SCHOTTKY

The LSTTL/MSI SN74LS175 is a high speed Quad D Flip-Flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW to HIGH clock transition. Both true and complemented outputs of each flip-flop are pro

丝印代码：LS175；HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

QUAD D FLIP-FLOP

The LSTTL /MSI SN54 /74LS175 is a high speed Quad D Flip-Flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW to HIGH clock transition. Both true and complemented outputs of each flip-flop ar

丝印代码：LS175；HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

丝印代码：LS175；HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

QUAD D FLIP-FLOP

The LSTTL /MSI SN54 /74LS175 is a high speed Quad D Flip-Flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW to HIGH clock transition. Both true and complemented outputs of each flip-flop ar

LOW POWER SCHOTTKY

The LSTTL/MSI SN74LS175 is a high speed Quad D Flip-Flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW to HIGH clock transition. Both true and complemented outputs of each flip-flop are pro

丝印代码：74LS175；HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

丝印代码：74LS175；HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

4-BY-4 REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS

文件：453.58 Kbytes Page：12 Pages

4-BY-4 REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS

文件：795.32 Kbytes Page：23 Pages

4-BY-4 REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS

文件：795.32 Kbytes Page：23 Pages

4-BY-4 REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS

文件：453.58 Kbytes Page：12 Pages

4-BY-4 REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS

文件：453.58 Kbytes Page：12 Pages

4-BY-4 REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS

文件：795.32 Kbytes Page：23 Pages

QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

文件：127.41 Kbytes Page：4 Pages

QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

文件：127.41 Kbytes Page：4 Pages

QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

文件：127.41 Kbytes Page：4 Pages

4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

文件：562.82 Kbytes Page：19 Pages

4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

文件：562.82 Kbytes Page：19 Pages

4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

文件：497.3 Kbytes Page：20 Pages

4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

文件：562.82 Kbytes Page：19 Pages

4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

文件：562.82 Kbytes Page：19 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：主复位 包装：管件 描述：IC FF D-TYPE SNGL 4BIT 16SOIC 集成电路（IC） 触发器

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：主复位 包装：管件 描述：IC FF D-TYPE SNGL 4BIT 16SOIC 集成电路（IC） 触发器

4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

文件：562.82 Kbytes Page：19 Pages

4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

文件：562.82 Kbytes Page：19 Pages

4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

文件：497.3 Kbytes Page：20 Pages

4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

文件：497.3 Kbytes Page：20 Pages