DUAL 4-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER

Controlled Baseline − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −40°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree† 3-State Version of ’HC153 Wide Operating Voltage Ran

DUAL 4-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER WITH 3-STATE OUTPUTS

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封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC MULTIPLEXER 2 X 4:1 16SOIC 集成电路（IC） 信号开关，多路复用器，解码器

DUAL 4-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER

Controlled Baseline − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −40°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree† 3-State Version of ’HC153 Wide Operating Voltage Ran

Dual 4-input multiplexer; 3-state

Dual 4-input multiplexer; 3-state

1. General description The 74HC253; 74HCT253 is a dual 4-bit multiplexer, each with four binary inputs (nI0 to nI3), an output enable input (nOE) and shared select inputs (S0 and S1). One of the four binary inputs is selected by the select inputs and routed to the output nY. A HIGH on nOE cause

Dual 4-input multiplexer; 3-state

GENERAL DESCRIPTION The 74HC/HCT253 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Non-inverting data path • 3-state outputs for bus interface • and multiplex e

Dual 4-input multiplexer; 3-state

1. General description The 74HC253; 74HCT253 is a dual 4-bit multiplexer, each with four binary inputs (nI0 to nI3), an output enable input (nOE) and shared select inputs (S0 and S1). One of the four binary inputs is selected by the select inputs and routed to the output nY. A HIGH on nOE cause

Dual 4-input multiplexer; 3-state

GENERAL DESCRIPTION The 74HC/HCT253 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Non-inverting data path • 3-state outputs for bus interface • and multiplex e