Dual 4-input multiplexer; 3-state

GENERAL DESCRIPTION The 74HC/HCT253 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Non-inverting data path • 3-state outputs for bus interface • and multiplex e

Dual 4-input multiplexer; 3-state

1. General description The 74HC253; 74HCT253 is a dual 4-bit multiplexer, each with four binary inputs (nI0 to nI3), an output enable input (nOE) and shared select inputs (S0 and S1). One of the four binary inputs is selected by the select inputs and routed to the output nY. A HIGH on nOE cause

Dual 4-input multiplexer; 3-state

1. General description The 74HC253; 74HCT253 is a dual 4-bit multiplexer, each with four binary inputs (nI0 to nI3), an output enable input (nOE) and shared select inputs (S0 and S1). One of the four binary inputs is selected by the select inputs and routed to the output nY. A HIGH on nOE cause

Dual 4-input multiplexer; 3-state

GENERAL DESCRIPTION The 74HC/HCT253 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Non-inverting data path • 3-state outputs for bus interface • and multiplex e

Dual 4-input multiplexer; 3-state

Dual 4-input multiplexer; 3-state

1. General description The 74HC253; 74HCT253 is a dual 4-bit multiplexer, each with four binary inputs (nI0 to nI3), an output enable input (nOE) and shared select inputs (S0 and S1). One of the four binary inputs is selected by the select inputs and routed to the output nY. A HIGH on nOE cause

Dual 4-input multiplexer; 3-state

GENERAL DESCRIPTION The 74HC/HCT253 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Non-inverting data path • 3-state outputs for bus interface • and multiplex e